Commit f698d314 authored by Russell King (Oracle)'s avatar Russell King (Oracle)
Browse files

Merge branches 'amba', 'cfi', 'clkdev' and 'misc' into for-linus

parents aff00427 7b749aad 8d532528 eebadafc

arch/arm/Kconfig

+20 −3
Original line number Diff line number Diff line
@@ -35,6 +35,7 @@ config ARM 
	select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX

	select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7

	select ARCH_SUPPORTS_ATOMIC_RMW

	select ARCH_SUPPORTS_CFI_CLANG

	select ARCH_SUPPORTS_HUGETLBFS if ARM_LPAE

	select ARCH_SUPPORTS_PER_VMA_LOCK

	select ARCH_USE_BUILTIN_BSWAP
@@ -1233,9 +1234,9 @@ config HIGHPTE 
	  consumed by page tables.  Setting this option will allow

	  user-space 2nd level page tables to reside in high memory.



config CPU_SW_DOMAIN_PAN

	bool "Enable use of CPU domains to implement privileged no-access"

	depends on MMU && !ARM_LPAE

config ARM_PAN

	bool "Enable privileged no-access"

	depends on MMU

	default y

	help

	  Increase kernel security by ensuring that normal kernel accesses
@@ -1244,10 +1245,26 @@ config CPU_SW_DOMAIN_PAN 
	  by ensuring that magic values (such as LIST_POISON) will always

	  fault when dereferenced.



	  The implementation uses CPU domains when !CONFIG_ARM_LPAE and

	  disabling of TTBR0 page table walks with CONFIG_ARM_LPAE.



config CPU_SW_DOMAIN_PAN

	def_bool y

	depends on ARM_PAN && !ARM_LPAE

	help

	  Enable use of CPU domains to implement privileged no-access.



	  CPUs with low-vector mappings use a best-efforts implementation.

	  Their lower 1MB needs to remain accessible for the vectors, but

	  the remainder of userspace will become appropriately inaccessible.



config CPU_TTBR0_PAN

	def_bool y

	depends on ARM_PAN && ARM_LPAE

	help

	  Enable privileged no-access by disabling TTBR0 page table walks when

	  running in kernel mode.



config HW_PERF_EVENTS

	def_bool y

	depends on ARM_PMU

arch/arm/include/asm/assembler.h

+1 −0
Original line number Diff line number Diff line
@@ -21,6 +21,7 @@ 
#include <asm/opcodes-virt.h>

#include <asm/asm-offsets.h>

#include <asm/page.h>

#include <asm/pgtable.h>

#include <asm/thread_info.h>

#include <asm/uaccess-asm.h>

arch/arm/include/asm/glue-cache.h

+9 −19
Original line number Diff line number Diff line
@@ -118,6 +118,10 @@ 
# define MULTI_CACHE 1

#endif



#ifdef CONFIG_CPU_CACHE_NOP

#  define MULTI_CACHE 1

#endif



#if defined(CONFIG_CPU_V7M)

#  define MULTI_CACHE 1

#endif
@@ -126,29 +130,15 @@ 
#error Unknown cache maintenance model

#endif



#ifndef __ASSEMBLER__

static inline void nop_flush_icache_all(void) { }

static inline void nop_flush_kern_cache_all(void) { }

static inline void nop_flush_kern_cache_louis(void) { }

static inline void nop_flush_user_cache_all(void) { }

static inline void nop_flush_user_cache_range(unsigned long a,

		unsigned long b, unsigned int c) { }



static inline void nop_coherent_kern_range(unsigned long a, unsigned long b) { }

static inline int nop_coherent_user_range(unsigned long a,

		unsigned long b) { return 0; }

static inline void nop_flush_kern_dcache_area(void *a, size_t s) { }



static inline void nop_dma_flush_range(const void *a, const void *b) { }



static inline void nop_dma_map_area(const void *s, size_t l, int f) { }

static inline void nop_dma_unmap_area(const void *s, size_t l, int f) { }

#endif



#ifndef MULTI_CACHE

#define __cpuc_flush_icache_all		__glue(_CACHE,_flush_icache_all)

#define __cpuc_flush_kern_all		__glue(_CACHE,_flush_kern_cache_all)

/* This function only has a dedicated assembly callback on the v7 cache */

#ifdef CONFIG_CPU_CACHE_V7

#define __cpuc_flush_kern_louis		__glue(_CACHE,_flush_kern_cache_louis)

#else

#define __cpuc_flush_kern_louis		__glue(_CACHE,_flush_kern_cache_all)

#endif

#define __cpuc_flush_user_all		__glue(_CACHE,_flush_user_cache_all)

#define __cpuc_flush_user_range		__glue(_CACHE,_flush_user_cache_range)

#define __cpuc_coherent_kern_range	__glue(_CACHE,_coherent_kern_range)

arch/arm/include/asm/hw_breakpoint.h

+1 −0
Original line number Diff line number Diff line
@@ -84,6 +84,7 @@ static inline void decode_ctrl_reg(u32 reg, 
#define ARM_DSCR_MOE(x)			((x >> 2) & 0xf)

#define ARM_ENTRY_BREAKPOINT		0x1

#define ARM_ENTRY_ASYNC_WATCHPOINT	0x2

#define ARM_ENTRY_CFI_BREAKPOINT	0x3

#define ARM_ENTRY_SYNC_WATCHPOINT	0xa



/* DSCR monitor/halting bits. */

arch/arm/include/asm/pgtable-3level-hwdef.h

+26 −0
Original line number Diff line number Diff line
@@ -74,6 +74,7 @@ 
#define PHYS_MASK_SHIFT		(40)

#define PHYS_MASK		((1ULL << PHYS_MASK_SHIFT) - 1)



#ifndef CONFIG_CPU_TTBR0_PAN

/*

 * TTBR0/TTBR1 split (PAGE_OFFSET):

 *   0x40000000: T0SZ = 2, T1SZ = 0 (not used)
@@ -93,5 +94,30 @@ 
#endif



#define TTBR1_SIZE	(((PAGE_OFFSET >> 30) - 1) << 16)

#else

/*

 * With CONFIG_CPU_TTBR0_PAN enabled, TTBR1 is only used during uaccess

 * disabled regions when TTBR0 is disabled.

 */

#define TTBR1_OFFSET	0			/* pointing to swapper_pg_dir */

#define TTBR1_SIZE	0			/* TTBR1 size controlled via TTBCR.T0SZ */

#endif



/*

 * TTBCR register bits.

 */

#define TTBCR_EAE		(1 << 31)

#define TTBCR_IMP		(1 << 30)

#define TTBCR_SH1_MASK		(3 << 28)

#define TTBCR_ORGN1_MASK	(3 << 26)

#define TTBCR_IRGN1_MASK	(3 << 24)

#define TTBCR_EPD1		(1 << 23)

#define TTBCR_A1		(1 << 22)

#define TTBCR_T1SZ_MASK		(7 << 16)

#define TTBCR_SH0_MASK		(3 << 12)

#define TTBCR_ORGN0_MASK	(3 << 10)

#define TTBCR_IRGN0_MASK	(3 << 8)

#define TTBCR_EPD0		(1 << 7)

#define TTBCR_T0SZ_MASK		(7 << 0)



#endif