Commit f7696ded authored by Matt Roper's avatar Matt Roper
Browse files

drm/i915/xelpg: Call Xe_LPG workaround functions based on IP version 



Although some of our Xe_LPG workarounds were already being applied based
on IP version correctly, others were matching on MTL as a base platform,
which is incorrect.  Although MTL is the only platform right now that
uses Xe_LPG IP, this may not always be the case.  If a future platform
re-uses this graphics IP, the same workarounds should be applied, even
if it isn't a "MTL" platform.

We were also incorrectly applying Xe_LPG workarounds/tuning to the
Xe_LPM+ media IP in one or two places; we should make sure that we don't
try to apply graphics workarounds to the media GT and vice versa where
they don't belong.  A new helper macro IS_GT_IP_RANGE() is added to help
ensure this is handled properly -- it checks that the GT matches the IP
type being tested as well as the IP version falling in the proper range.

Note that many of the stepping-based workarounds are still incorrectly
checking for a MTL base platform; that will be remedied in a later
patch.

v2:
 - Rework macro into a slightly more generic IS_GT_IP_RANGE() that can
   be used for either GFX or MEDIA checks.

v3:
 - Switch back to separate macros for gfx and media.  (Jani)
 - Move macro to intel_gt.h.  (Andi)

Cc: Gustavo Sousa <gustavo.sousa@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Andi Shyti <andi.shyti@linux.intel.com>
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Reviewed-by: default avatarAndi Shyti <andi.shyti@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230821180619.650007-14-matthew.d.roper@intel.com
parent ea2f1556

drivers/gpu/drm/i915/gt/intel_gt.h

+11 −0
Original line number Diff line number Diff line
@@ -14,6 +14,17 @@ 
struct drm_i915_private;

struct drm_printer;



/*

 * Check that the GT is a graphics GT and has an IP version within the

 * specified range (inclusive).

 */

#define IS_GFX_GT_IP_RANGE(gt, from, until) ( \

	BUILD_BUG_ON_ZERO((from) < IP_VER(2, 0)) + \

	BUILD_BUG_ON_ZERO((until) < (from)) + \

	((gt)->type != GT_MEDIA && \

	 GRAPHICS_VER_FULL((gt)->i915) >= (from) && \

	 GRAPHICS_VER_FULL((gt)->i915) <= (until)))



#define GT_TRACE(gt, fmt, ...) do {					\

	const struct intel_gt *gt__ __maybe_unused = (gt);		\

	GEM_TRACE("%s " fmt, dev_name(gt__->i915->drm.dev),		\

drivers/gpu/drm/i915/gt/intel_workarounds.c

+20 −18
Original line number Diff line number Diff line
@@ -778,7 +778,7 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine, 
	wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE);

}



static void mtl_ctx_gt_tuning_init(struct intel_engine_cs *engine,

static void xelpg_ctx_gt_tuning_init(struct intel_engine_cs *engine,

				     struct i915_wa_list *wal)

{

	struct drm_i915_private *i915 = engine->i915;
@@ -790,12 +790,12 @@ static void mtl_ctx_gt_tuning_init(struct intel_engine_cs *engine, 
		wa_add(wal, DRAW_WATERMARK, VERT_WM_VAL, 0x3FF, 0, false);

}



static void mtl_ctx_workarounds_init(struct intel_engine_cs *engine,

static void xelpg_ctx_workarounds_init(struct intel_engine_cs *engine,

				       struct i915_wa_list *wal)

{

	struct drm_i915_private *i915 = engine->i915;



	mtl_ctx_gt_tuning_init(engine, wal);

	xelpg_ctx_gt_tuning_init(engine, wal);



	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||

	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
@@ -904,8 +904,8 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine, 
	if (engine->class != RENDER_CLASS)

		goto done;



	if (IS_METEORLAKE(i915))

		mtl_ctx_workarounds_init(engine, wal);

	if (IS_GFX_GT_IP_RANGE(engine->gt, IP_VER(12, 70), IP_VER(12, 71)))

		xelpg_ctx_workarounds_init(engine, wal);

	else if (IS_PONTEVECCHIO(i915))

		; /* noop; none at this time */

	else if (IS_DG2(i915))
@@ -1684,10 +1684,8 @@ xelpmp_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 
 */

static void gt_tuning_settings(struct intel_gt *gt, struct i915_wa_list *wal)

{

	if (IS_METEORLAKE(gt->i915)) {

		if (gt->type != GT_MEDIA)

	if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71))) {

		wa_mcr_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS);



		wa_mcr_write_or(wal, XEHP_SQCM, EN_32B_ACCESS);

	}
@@ -1719,7 +1717,7 @@ gt_init_workarounds(struct intel_gt *gt, struct i915_wa_list *wal) 
		return;

	}



	if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))

	if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)))

		xelpg_gt_workarounds_init(gt, wal);

	else if (IS_PONTEVECCHIO(i915))

		pvc_gt_workarounds_init(gt, wal);
@@ -2168,7 +2166,7 @@ static void pvc_whitelist_build(struct intel_engine_cs *engine) 
	blacklist_trtt(engine);

}



static void mtl_whitelist_build(struct intel_engine_cs *engine)

static void xelpg_whitelist_build(struct intel_engine_cs *engine)

{

	struct i915_wa_list *w = &engine->whitelist;
@@ -2190,8 +2188,10 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine) 


	wa_init_start(w, engine->gt, "whitelist", engine->name);



	if (IS_METEORLAKE(i915))

		mtl_whitelist_build(engine);

	if (engine->gt->type == GT_MEDIA)

		; /* none yet */

	else if (IS_GFX_GT_IP_RANGE(engine->gt, IP_VER(12, 70), IP_VER(12, 71)))

		xelpg_whitelist_build(engine);

	else if (IS_PONTEVECCHIO(i915))

		pvc_whitelist_build(engine);

	else if (IS_DG2(i915))
@@ -2791,10 +2791,12 @@ ccs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 
 * function invoked by __intel_engine_init_ctx_wa().

 */

static void

add_render_compute_tuning_settings(struct drm_i915_private *i915,

add_render_compute_tuning_settings(struct intel_gt *gt,

				   struct i915_wa_list *wal)

{

	if (IS_METEORLAKE(i915) || IS_DG2(i915))

	struct drm_i915_private *i915 = gt->i915;



	if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)) || IS_DG2(i915))

		wa_mcr_write_clr_set(wal, RT_CTRL, STACKID_CTRL, STACKID_CTRL_512);



	/*
@@ -2824,7 +2826,7 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li 
{

	struct drm_i915_private *i915 = engine->i915;



	add_render_compute_tuning_settings(i915, wal);

	add_render_compute_tuning_settings(engine->gt, wal);



	if (GRAPHICS_VER(i915) >= 11) {

		/* This is not a Wa (although referred to as