Commit f80e8944 authored by Thomas Zimmermann's avatar Thomas Zimmermann
Browse files

drm/amdgpu: Do not implement mode_set_base_atomic callback 



Remove all implementations of the CRTC helper mode_set_base_atomic
from amdgpu. It pretends to provide mode setting for kdb debugging,
but has been broken for some time.

Kdb output has been supported only for non-atomic mode setting since
commit 9c79e0b1 ("drm/fb-helper: Give up on kgdb for atomic drivers")
from 2017.

While amdgpu provides non-atomic mode setting for some devices, kdb
assumes that the GEM buffer object is at a fixed location in video
memory. This has not been the case since commit 087451f3 ("drm/amdgpu:
use generic fb helpers instead of setting up AMD own's.") from 2021.
Fbdev-ttm helpers use a shadow buffer with a movable GEM buffer object.
Triggering kdb does not update the display.

Hence remove the whole kdb support from amdgpu.

Signed-off-by: default avatarThomas Zimmermann <tzimmermann@suse.de>
Acked-by: default avatarChristian König <christian.koenig@amd.com>
Acked-by: default avatarSimona Vetter <simona.vetter@ffwll.ch>
Acked-by: default avatarDaniel Thompson (RISCstar) <danielt@kernel.org>
Link: https://patch.msgid.link/20251125130634.1080966-2-tzimmermann@suse.de
parent b1ea3bab

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

+11 −24
Original line number Diff line number Diff line
@@ -1838,7 +1838,7 @@ static void dce_v10_0_grph_enable(struct drm_crtc *crtc, bool enable) 


static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc,

				     struct drm_framebuffer *fb,

				     int x, int y, int atomic)

				     int x, int y)

{

	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

	struct drm_device *dev = crtc->dev;
@@ -1855,14 +1855,11 @@ static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc, 
	bool bypass_lut = false;



	/* no fb bound */

	if (!atomic && !crtc->primary->fb) {

	if (!crtc->primary->fb) {

		DRM_DEBUG_KMS("No FB bound\n");

		return 0;

	}



	if (atomic)

		target_fb = fb;

	else

	target_fb = crtc->primary->fb;



	/* If atomic, assume fb object is pinned & idle & fenced and
@@ -1874,14 +1871,12 @@ static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc, 
	if (unlikely(r != 0))

		return r;



	if (!atomic) {

	abo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;

	r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM);

	if (unlikely(r != 0)) {

		amdgpu_bo_unreserve(abo);

		return -EINVAL;

	}

	}

	fb_location = amdgpu_bo_gpu_offset(abo);



	amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
@@ -2068,7 +2063,7 @@ static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc, 
	/* set pageflip to happen anywhere in vblank interval */

	WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);



	if (!atomic && fb && fb != crtc->primary->fb) {

	if (fb && fb != crtc->primary->fb) {

		abo = gem_to_amdgpu_bo(fb->obj[0]);

		r = amdgpu_bo_reserve(abo, true);

		if (unlikely(r != 0))
@@ -2611,7 +2606,7 @@ static int dce_v10_0_crtc_mode_set(struct drm_crtc *crtc, 


	amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);

	amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);

	dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0);

	dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y);

	amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);

	amdgpu_atombios_crtc_scaler_setup(crtc);

	dce_v10_0_cursor_reset(crtc);
@@ -2659,14 +2654,7 @@ static bool dce_v10_0_crtc_mode_fixup(struct drm_crtc *crtc, 
static int dce_v10_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,

				  struct drm_framebuffer *old_fb)

{

	return dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0);

}



static int dce_v10_0_crtc_set_base_atomic(struct drm_crtc *crtc,

					 struct drm_framebuffer *fb,

					 int x, int y, enum mode_set_atomic state)

{

	return dce_v10_0_crtc_do_set_base(crtc, fb, x, y, 1);

	return dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y);

}



static const struct drm_crtc_helper_funcs dce_v10_0_crtc_helper_funcs = {
@@ -2674,7 +2662,6 @@ static const struct drm_crtc_helper_funcs dce_v10_0_crtc_helper_funcs = { 
	.mode_fixup = dce_v10_0_crtc_mode_fixup,

	.mode_set = dce_v10_0_crtc_mode_set,

	.mode_set_base = dce_v10_0_crtc_set_base,

	.mode_set_base_atomic = dce_v10_0_crtc_set_base_atomic,

	.prepare = dce_v10_0_crtc_prepare,

	.commit = dce_v10_0_crtc_commit,

	.disable = dce_v10_0_crtc_disable,

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

+11 −24
Original line number Diff line number Diff line
@@ -1876,7 +1876,7 @@ static void dce_v6_0_grph_enable(struct drm_crtc *crtc, bool enable) 


static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc,

				     struct drm_framebuffer *fb,

				     int x, int y, int atomic)

				     int x, int y)

{

	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

	struct drm_device *dev = crtc->dev;
@@ -1892,14 +1892,11 @@ static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc, 
	bool bypass_lut = false;



	/* no fb bound */

	if (!atomic && !crtc->primary->fb) {

	if (!crtc->primary->fb) {

		DRM_DEBUG_KMS("No FB bound\n");

		return 0;

	}



	if (atomic)

		target_fb = fb;

	else

	target_fb = crtc->primary->fb;



	/* If atomic, assume fb object is pinned & idle & fenced and
@@ -1911,14 +1908,12 @@ static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc, 
	if (unlikely(r != 0))

		return r;



	if (!atomic) {

	abo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;

	r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM);

	if (unlikely(r != 0)) {

		amdgpu_bo_unreserve(abo);

		return -EINVAL;

	}

	}

	fb_location = amdgpu_bo_gpu_offset(abo);



	amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
@@ -2083,7 +2078,7 @@ static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc, 
	/* set pageflip to happen anywhere in vblank interval */

	WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);



	if (!atomic && fb && fb != crtc->primary->fb) {

	if (fb && fb != crtc->primary->fb) {

		abo = gem_to_amdgpu_bo(fb->obj[0]);

		r = amdgpu_bo_reserve(abo, true);

		if (unlikely(r != 0))
@@ -2578,7 +2573,7 @@ static int dce_v6_0_crtc_mode_set(struct drm_crtc *crtc, 


	amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);

	amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);

	dce_v6_0_crtc_do_set_base(crtc, old_fb, x, y, 0);

	dce_v6_0_crtc_do_set_base(crtc, old_fb, x, y);

	amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);

	amdgpu_atombios_crtc_scaler_setup(crtc);

	dce_v6_0_cursor_reset(crtc);
@@ -2626,14 +2621,7 @@ static bool dce_v6_0_crtc_mode_fixup(struct drm_crtc *crtc, 
static int dce_v6_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,

				  struct drm_framebuffer *old_fb)

{

	return dce_v6_0_crtc_do_set_base(crtc, old_fb, x, y, 0);

}



static int dce_v6_0_crtc_set_base_atomic(struct drm_crtc *crtc,

					 struct drm_framebuffer *fb,

					 int x, int y, enum mode_set_atomic state)

{

	return dce_v6_0_crtc_do_set_base(crtc, fb, x, y, 1);

	return dce_v6_0_crtc_do_set_base(crtc, old_fb, x, y);

}



static const struct drm_crtc_helper_funcs dce_v6_0_crtc_helper_funcs = {
@@ -2641,7 +2629,6 @@ static const struct drm_crtc_helper_funcs dce_v6_0_crtc_helper_funcs = { 
	.mode_fixup = dce_v6_0_crtc_mode_fixup,

	.mode_set = dce_v6_0_crtc_mode_set,

	.mode_set_base = dce_v6_0_crtc_set_base,

	.mode_set_base_atomic = dce_v6_0_crtc_set_base_atomic,

	.prepare = dce_v6_0_crtc_prepare,

	.commit = dce_v6_0_crtc_commit,

	.disable = dce_v6_0_crtc_disable,

drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

+11 −24
Original line number Diff line number Diff line
@@ -1785,7 +1785,7 @@ static void dce_v8_0_grph_enable(struct drm_crtc *crtc, bool enable) 


static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc,

				     struct drm_framebuffer *fb,

				     int x, int y, int atomic)

				     int x, int y)

{

	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

	struct drm_device *dev = crtc->dev;
@@ -1802,14 +1802,11 @@ static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc, 
	bool bypass_lut = false;



	/* no fb bound */

	if (!atomic && !crtc->primary->fb) {

	if (!crtc->primary->fb) {

		DRM_DEBUG_KMS("No FB bound\n");

		return 0;

	}



	if (atomic)

		target_fb = fb;

	else

	target_fb = crtc->primary->fb;



	/* If atomic, assume fb object is pinned & idle & fenced and
@@ -1821,14 +1818,12 @@ static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc, 
	if (unlikely(r != 0))

		return r;



	if (!atomic) {

	abo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;

	r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM);

	if (unlikely(r != 0)) {

		amdgpu_bo_unreserve(abo);

		return -EINVAL;

	}

	}

	fb_location = amdgpu_bo_gpu_offset(abo);



	amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
@@ -1995,7 +1990,7 @@ static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc, 
	/* set pageflip to happen anywhere in vblank interval */

	WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);



	if (!atomic && fb && fb != crtc->primary->fb) {

	if (fb && fb != crtc->primary->fb) {

		abo = gem_to_amdgpu_bo(fb->obj[0]);

		r = amdgpu_bo_reserve(abo, true);

		if (unlikely(r != 0))
@@ -2537,7 +2532,7 @@ static int dce_v8_0_crtc_mode_set(struct drm_crtc *crtc, 


	amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);

	amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);

	dce_v8_0_crtc_do_set_base(crtc, old_fb, x, y, 0);

	dce_v8_0_crtc_do_set_base(crtc, old_fb, x, y);

	amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);

	amdgpu_atombios_crtc_scaler_setup(crtc);

	dce_v8_0_cursor_reset(crtc);
@@ -2585,14 +2580,7 @@ static bool dce_v8_0_crtc_mode_fixup(struct drm_crtc *crtc, 
static int dce_v8_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,

				  struct drm_framebuffer *old_fb)

{

	return dce_v8_0_crtc_do_set_base(crtc, old_fb, x, y, 0);

}



static int dce_v8_0_crtc_set_base_atomic(struct drm_crtc *crtc,

					 struct drm_framebuffer *fb,

					 int x, int y, enum mode_set_atomic state)

{

	return dce_v8_0_crtc_do_set_base(crtc, fb, x, y, 1);

	return dce_v8_0_crtc_do_set_base(crtc, old_fb, x, y);

}



static const struct drm_crtc_helper_funcs dce_v8_0_crtc_helper_funcs = {
@@ -2600,7 +2588,6 @@ static const struct drm_crtc_helper_funcs dce_v8_0_crtc_helper_funcs = { 
	.mode_fixup = dce_v8_0_crtc_mode_fixup,

	.mode_set = dce_v8_0_crtc_mode_set,

	.mode_set_base = dce_v8_0_crtc_set_base,

	.mode_set_base_atomic = dce_v8_0_crtc_set_base_atomic,

	.prepare = dce_v8_0_crtc_prepare,

	.commit = dce_v8_0_crtc_commit,

	.disable = dce_v8_0_crtc_disable,