Commit f827bcda authored by Rob Herring's avatar Rob Herring Committed by Will Deacon
Browse files

arm64: errata: Add Cortex-A510 speculative unprivileged load workaround 



Implement the workaround for ARM Cortex-A510 erratum 3117295. On an
affected Cortex-A510 core, a speculatively executed unprivileged load
might leak data from a privileged load via a cache side channel. The
issue only exists for loads within a translation regime with the same
translation (e.g. same ASID and VMID). Therefore, the issue only affects
the return to EL0.

The erratum and workaround are the same as ARM Cortex-A520 erratum
2966298, so reuse the existing workaround.

Cc: stable@vger.kernel.org
Signed-off-by: default avatarRob Herring <robh@kernel.org>
Reviewed-by: default avatarMark Rutland <mark.rutland@arm.com>
Link: https://lore.kernel.org/r/20240110-arm-errata-a510-v1-2-d02bc51aeeee@kernel.org


Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent 546b7cde

Documentation/arch/arm64/silicon-errata.rst

+2 −0
Original line number Diff line number Diff line
@@ -71,6 +71,8 @@ stable kernels. 
+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A510     | #2658417        | ARM64_ERRATUM_2658417       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A510     | #3117295        | ARM64_ERRATUM_3117295       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A520     | #2966298        | ARM64_ERRATUM_2966298       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A53      | #826319         | ARM64_ERRATUM_826319        |

arch/arm64/Kconfig

+14 −0
Original line number Diff line number Diff line
@@ -1054,6 +1054,20 @@ config ARM64_ERRATUM_2966298 


	  If unsure, say Y.



config ARM64_ERRATUM_3117295

	bool "Cortex-A510: 3117295: workaround for speculatively executed unprivileged load"

	select ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD

	default y

	help

	  This option adds the workaround for ARM Cortex-A510 erratum 3117295.



	  On an affected Cortex-A510 core, a speculatively executed unprivileged

	  load might leak data from a privileged level via a cache side channel.



	  Work around this problem by executing a TLBI before returning to EL0.



	  If unsure, say Y.



config CAVIUM_ERRATUM_22375

	bool "Cavium erratum 22375, 24313"

	default y

arch/arm64/kernel/cpu_errata.c

+15 −2
Original line number Diff line number Diff line
@@ -416,6 +416,19 @@ static struct midr_range broken_aarch32_aes[] = { 
};

#endif /* CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE */



#ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD

static const struct midr_range erratum_spec_unpriv_load_list[] = {

#ifdef CONFIG_ARM64_ERRATUM_3117295

	MIDR_ALL_VERSIONS(MIDR_CORTEX_A510),

#endif

#ifdef CONFIG_ARM64_ERRATUM_2966298

	/* Cortex-A520 r0p0 to r0p1 */

	MIDR_REV_RANGE(MIDR_CORTEX_A520, 0, 0, 1),

#endif

	{},

};

#endif



const struct arm64_cpu_capabilities arm64_errata[] = {

#ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE

	{
@@ -715,10 +728,10 @@ const struct arm64_cpu_capabilities arm64_errata[] = { 
#endif

#ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD

	{

		.desc = "ARM erratum 2966298",

		.desc = "ARM errata 2966298, 3117295",

		.capability = ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD,

		/* Cortex-A520 r0p0 - r0p1 */

		ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A520, 0, 0, 1),

		ERRATA_MIDR_RANGE_LIST(erratum_spec_unpriv_load_list),

	},

#endif

#ifdef CONFIG_AMPERE_ERRATUM_AC03_CPU_38