Commit f88f3575 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-next-2025-11-14' of... 

Merge tag 'drm-intel-next-2025-11-14' of https://gitlab.freedesktop.org/drm/i915/kernel

 into drm-next

drm/i915 feature pull #2 for v6.19:

Features and functionality:
- Add initial display support for Xe3p_LPD, display version 35 (Sai Teja, Matt
  R, Gustavo, Matt A, Ankit, Juha-pekka, Luca, Ravi Kumar)
- Compute LT PHY HDMI params when port clock not in predefined tables (Suraj)

Refactoring and cleanups:
- Refactor intel_frontbuffer split between i915, xe, and display (Ville)
- Clean up intel_de_wait_custom() usage (Ville)
- Unify display register polling interfaces (Ville)
- Finish removal of the expensive format info lookups (Ville)
- Cursor code cleanups (Ville)
- Convert intel_rom interfaces to struct drm_device (Jani)

Fixes:
- Fix uninitialized variable in DSI exec packet (Jonathan)
- Fix PIPEDMC logging (Alok Tiwari)
- Fix PSR pipe to vblank conversion (Jani)
- Fix intel_frontbuffer lifetime handling (Ville)
- Disable Panel Replay on DP MST for the time being (Imre)

Merges:
- Backmerge drm-next to get the drm_print.h changes (Jani)

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Jani Nikula <jani.nikula@intel.com>
Link: https://patch.msgid.link/b131309bb7310ab749f1770aa6e36fa8d6a82fa5@intel.com
parents 490fd933 b84befa3

drivers/gpu/drm/i915/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -156,6 +156,7 @@ gem-y += \ 
	gem/i915_gem_lmem.o \

	gem/i915_gem_mman.o \

	gem/i915_gem_object.o \

	gem/i915_gem_object_frontbuffer.o \

	gem/i915_gem_pages.o \

	gem/i915_gem_phys.o \

	gem/i915_gem_pm.o \

drivers/gpu/drm/i915/display/hsw_ips.c

+2 −2
Original line number Diff line number Diff line
@@ -56,7 +56,7 @@ static void hsw_ips_enable(const struct intel_crtc_state *crtc_state) 
		 * the HW state readout code will complain that the expected

		 * IPS_CTL value is not the one we read.

		 */

		if (intel_de_wait_for_set(display, IPS_CTL, IPS_ENABLE, 50))

		if (intel_de_wait_for_set_ms(display, IPS_CTL, IPS_ENABLE, 50))

			drm_err(display->drm,

				"Timed out waiting for IPS enable\n");

	}
@@ -78,7 +78,7 @@ bool hsw_ips_disable(const struct intel_crtc_state *crtc_state) 
		 * 42ms timeout value leads to occasional timeouts so use 100ms

		 * instead.

		 */

		if (intel_de_wait_for_clear(display, IPS_CTL, IPS_ENABLE, 100))

		if (intel_de_wait_for_clear_ms(display, IPS_CTL, IPS_ENABLE, 100))

			drm_err(display->drm,

				"Timed out waiting for IPS disable\n");

	} else {

drivers/gpu/drm/i915/display/i9xx_plane.c

+14 −18
Original line number Diff line number Diff line
@@ -754,10 +754,9 @@ static bool i9xx_plane_get_hw_state(struct intel_plane *plane, 


static unsigned int

hsw_primary_max_stride(struct intel_plane *plane,

		       u32 pixel_format, u64 modifier,

		       unsigned int rotation)

		       const struct drm_format_info *info,

		       u64 modifier, unsigned int rotation)

{

	const struct drm_format_info *info = drm_format_info(pixel_format);

	int cpp = info->cpp[0];



	/* Limit to 8k pixels to guarantee OFFSET.x doesn't get too big. */
@@ -766,10 +765,9 @@ hsw_primary_max_stride(struct intel_plane *plane, 


static unsigned int

ilk_primary_max_stride(struct intel_plane *plane,

		       u32 pixel_format, u64 modifier,

		       unsigned int rotation)

		       const struct drm_format_info *info,

		       u64 modifier, unsigned int rotation)

{

	const struct drm_format_info *info = drm_format_info(pixel_format);

	int cpp = info->cpp[0];



	/* Limit to 4k pixels to guarantee TILEOFF.x doesn't get too big. */
@@ -781,10 +779,9 @@ ilk_primary_max_stride(struct intel_plane *plane, 


unsigned int

i965_plane_max_stride(struct intel_plane *plane,

		      u32 pixel_format, u64 modifier,

		      unsigned int rotation)

		      const struct drm_format_info *info,

		      u64 modifier, unsigned int rotation)

{

	const struct drm_format_info *info = drm_format_info(pixel_format);

	int cpp = info->cpp[0];



	/* Limit to 4k pixels to guarantee TILEOFF.x doesn't get too big. */
@@ -796,8 +793,8 @@ i965_plane_max_stride(struct intel_plane *plane, 


static unsigned int

i915_plane_max_stride(struct intel_plane *plane,

		      u32 pixel_format, u64 modifier,

		      unsigned int rotation)

		      const struct drm_format_info *info,

		      u64 modifier, unsigned int rotation)

{

	if (modifier == I915_FORMAT_MOD_X_TILED)

		return 8 * 1024;
@@ -807,8 +804,8 @@ i915_plane_max_stride(struct intel_plane *plane, 


static unsigned int

i8xx_plane_max_stride(struct intel_plane *plane,

		      u32 pixel_format, u64 modifier,

		      unsigned int rotation)

		      const struct drm_format_info *info,

		      u64 modifier, unsigned int rotation)

{

	if (plane->i9xx_plane == PLANE_C)

		return 4 * 1024;
@@ -1191,10 +1188,8 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc, 
	val = intel_de_read(display, DSPCNTR(display, i9xx_plane));



	if (DISPLAY_VER(display) >= 4) {

		if (val & DISP_TILED) {

			plane_config->tiling = I915_TILING_X;

		if (val & DISP_TILED)

			fb->modifier = I915_FORMAT_MOD_X_TILED;

		}



		if (val & DISP_ROTATE_180)

			plane_config->rotation = DRM_MODE_ROTATE_180;
@@ -1206,14 +1201,15 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc, 


	pixel_format = val & DISP_FORMAT_MASK;

	fourcc = i9xx_format_to_fourcc(pixel_format);

	fb->format = drm_format_info(fourcc);



	fb->format = drm_get_format_info(display->drm, fourcc, fb->modifier);



	if (display->platform.haswell || display->platform.broadwell) {

		offset = intel_de_read(display,

				       DSPOFFSET(display, i9xx_plane));

		base = intel_de_read(display, DSPSURF(display, i9xx_plane)) & DISP_ADDR_MASK;

	} else if (DISPLAY_VER(display) >= 4) {

		if (plane_config->tiling)

		if (fb->modifier == I915_FORMAT_MOD_X_TILED)

			offset = intel_de_read(display,

					       DSPTILEOFF(display, i9xx_plane));

		else

drivers/gpu/drm/i915/display/i9xx_plane.h

+3 −2
Original line number Diff line number Diff line
@@ -9,6 +9,7 @@ 
#include <linux/types.h>



enum pipe;

struct drm_format_info;

struct drm_framebuffer;

struct intel_crtc;

struct intel_display;
@@ -18,8 +19,8 @@ struct intel_plane_state; 


#ifdef I915

unsigned int i965_plane_max_stride(struct intel_plane *plane,

				   u32 pixel_format, u64 modifier,

				   unsigned int rotation);

				   const struct drm_format_info *info,

				   u64 modifier, unsigned int rotation);

unsigned int vlv_plane_min_alignment(struct intel_plane *plane,

				     const struct drm_framebuffer *fb,

				     int colot_plane);

drivers/gpu/drm/i915/display/icl_dsi.c

+16 −19
Original line number Diff line number Diff line
@@ -148,9 +148,9 @@ static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder) 
	for_each_dsi_port(port, intel_dsi->ports) {

		dsi_trans = dsi_port_to_transcoder(port);



		ret = intel_de_wait_custom(display, DSI_LP_MSG(dsi_trans),

					   LPTX_IN_PROGRESS, 0,

					   20, 0, NULL);

		ret = intel_de_wait_for_clear_us(display,

						 DSI_LP_MSG(dsi_trans),

						 LPTX_IN_PROGRESS, 20);

		if (ret)

			drm_err(display->drm, "LPTX bit not cleared\n");

	}
@@ -534,9 +534,8 @@ static void gen11_dsi_enable_ddi_buffer(struct intel_encoder *encoder) 
	for_each_dsi_port(port, intel_dsi->ports) {

		intel_de_rmw(display, DDI_BUF_CTL(port), 0, DDI_BUF_CTL_ENABLE);



		ret = intel_de_wait_custom(display, DDI_BUF_CTL(port),

					   DDI_BUF_IS_IDLE, 0,

					   500, 0, NULL);

		ret = intel_de_wait_for_clear_us(display, DDI_BUF_CTL(port),

						 DDI_BUF_IS_IDLE, 500);

		if (ret)

			drm_err(display->drm, "DDI port:%c buffer idle\n",

				port_name(port));
@@ -857,9 +856,9 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder, 


		dsi_trans = dsi_port_to_transcoder(port);



		ret = intel_de_wait_custom(display, DSI_TRANS_FUNC_CONF(dsi_trans),

					   LINK_READY, LINK_READY,

					   2500, 0, NULL);

		ret = intel_de_wait_for_set_us(display,

					       DSI_TRANS_FUNC_CONF(dsi_trans),

					       LINK_READY, 2500);

		if (ret)

			drm_err(display->drm, "DSI link not ready\n");

	}
@@ -1048,7 +1047,7 @@ static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder) 
			     TRANSCONF_ENABLE);



		/* wait for transcoder to be enabled */

		if (intel_de_wait_for_set(display, TRANSCONF(display, dsi_trans),

		if (intel_de_wait_for_set_ms(display, TRANSCONF(display, dsi_trans),

					     TRANSCONF_STATE_ENABLE, 10))

			drm_err(display->drm,

				"DSI transcoder not enabled\n");
@@ -1317,7 +1316,7 @@ static void gen11_dsi_disable_transcoder(struct intel_encoder *encoder) 
			     TRANSCONF_ENABLE, 0);



		/* wait for transcoder to be disabled */

		if (intel_de_wait_for_clear(display, TRANSCONF(display, dsi_trans),

		if (intel_de_wait_for_clear_ms(display, TRANSCONF(display, dsi_trans),

					       TRANSCONF_STATE_ENABLE, 50))

			drm_err(display->drm,

				"DSI trancoder not disabled\n");
@@ -1358,9 +1357,8 @@ static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder) 
		tmp &= ~LINK_ULPS_TYPE_LP11;

		intel_de_write(display, DSI_LP_MSG(dsi_trans), tmp);



		ret = intel_de_wait_custom(display, DSI_LP_MSG(dsi_trans),

					   LINK_IN_ULPS, LINK_IN_ULPS,

					   10, 0, NULL);

		ret = intel_de_wait_for_set_us(display, DSI_LP_MSG(dsi_trans),

					       LINK_IN_ULPS, 10);

		if (ret)

			drm_err(display->drm, "DSI link not in ULPS\n");

	}
@@ -1395,9 +1393,8 @@ static void gen11_dsi_disable_port(struct intel_encoder *encoder) 
	for_each_dsi_port(port, intel_dsi->ports) {

		intel_de_rmw(display, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, 0);



		ret = intel_de_wait_custom(display, DDI_BUF_CTL(port),

					   DDI_BUF_IS_IDLE, DDI_BUF_IS_IDLE,

					   8, 0, NULL);

		ret = intel_de_wait_for_set_us(display, DDI_BUF_CTL(port),

					       DDI_BUF_IS_IDLE, 8);



		if (ret)

			drm_err(display->drm,