Commit f92bb743 authored by Peter Griffin's avatar Peter Griffin Committed by Martin K. Petersen
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scsi: ufs: exynos: Disable iocc if dma-coherent property isn't set



If dma-coherent property isn't set then descriptors are non-cacheable
and the iocc shareability bits should be disabled. Without this UFS can
end up in an incompatible configuration and suffer from random cache
related stability issues.

Suggested-by: default avatarBart Van Assche <bvanassche@acm.org>
Fixes: cc52e153 ("scsi: ufs: ufs-exynos: Support ExynosAuto v9 UFS")
Signed-off-by: default avatarPeter Griffin <peter.griffin@linaro.org>
Link: https://lore.kernel.org/r/20250319-exynos-ufs-stability-fixes-v2-3-96722cc2ba1b@linaro.org


Cc: Chanho Park <chanho61.park@samsung.com>
Cc: stable@vger.kernel.org
Reviewed-by: default avatarBart Van Assche <bvanassche@acm.org>
Signed-off-by: default avatarMartin K. Petersen <martin.petersen@oracle.com>
parent 68f5ef7e
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+13 −4
Original line number Diff line number Diff line
@@ -214,8 +214,8 @@ static int exynos_ufs_shareability(struct exynos_ufs *ufs)
	/* IO Coherency setting */
	if (ufs->sysreg) {
		return regmap_update_bits(ufs->sysreg,
					  ufs->shareability_reg_offset,
					  ufs->iocc_mask, ufs->iocc_mask);
					  ufs->iocc_offset,
					  ufs->iocc_mask, ufs->iocc_val);
	}

	return 0;
@@ -1173,13 +1173,22 @@ static int exynos_ufs_parse_dt(struct device *dev, struct exynos_ufs *ufs)
		ufs->sysreg = NULL;
	else {
		if (of_property_read_u32_index(np, "samsung,sysreg", 1,
					       &ufs->shareability_reg_offset)) {
					       &ufs->iocc_offset)) {
			dev_warn(dev, "can't get an offset from sysreg. Set to default value\n");
			ufs->shareability_reg_offset = UFS_SHAREABILITY_OFFSET;
			ufs->iocc_offset = UFS_SHAREABILITY_OFFSET;
		}
	}

	ufs->iocc_mask = ufs->drv_data->iocc_mask;
	/*
	 * no 'dma-coherent' property means the descriptors are
	 * non-cacheable so iocc shareability should be disabled.
	 */
	if (of_dma_is_coherent(dev->of_node))
		ufs->iocc_val = ufs->iocc_mask;
	else
		ufs->iocc_val = 0;

	ufs->pclk_avail_min = PCLK_AVAIL_MIN;
	ufs->pclk_avail_max = PCLK_AVAIL_MAX;

+2 −1
Original line number Diff line number Diff line
@@ -231,8 +231,9 @@ struct exynos_ufs {
	ktime_t entry_hibern8_t;
	const struct exynos_ufs_drv_data *drv_data;
	struct regmap *sysreg;
	u32 shareability_reg_offset;
	u32 iocc_offset;
	u32 iocc_mask;
	u32 iocc_val;

	u32 opts;
#define EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL		BIT(0)