Commit f98eded9 authored by Lorenzo Bianconi's avatar Lorenzo Bianconi Committed by Stephen Boyd
Browse files

clk: en7523: fix estimation of fixed rate for EN7581 



Introduce en7581_base_clks array in order to define per-SoC fixed-rate
clock parameters and fix wrong parameters for emi, npu and crypto EN7581
clocks

Fixes: 66bc4732 ("clk: en7523: Add EN7581 support")
Signed-off-by: default avatarLorenzo Bianconi <lorenzo@kernel.org>
Link: https://lore.kernel.org/r/20241112-clk-en7581-syscon-v2-5-8ada5e394ae4@kernel.org


Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent f72fc220

drivers/clk/clk-en7523.c

+103 −2
Original line number Diff line number Diff line
@@ -37,6 +37,7 @@ 
#define REG_NP_SCU_SSTR			0x9c

#define REG_PCIE_XSI0_SEL_MASK		GENMASK(14, 13)

#define REG_PCIE_XSI1_SEL_MASK		GENMASK(12, 11)

#define REG_CRYPTO_CLKSRC2		0x20c



#define REG_RST_CTRL2			0x00

#define REG_RST_CTRL1			0x04
@@ -89,6 +90,10 @@ static const u32 emi_base[] = { 333000000, 400000000 }; 
static const u32 bus_base[] = { 500000000, 540000000 };

static const u32 slic_base[] = { 100000000, 3125000 };

static const u32 npu_base[] = { 333000000, 400000000, 500000000 };

/* EN7581 */

static const u32 emi7581_base[] = { 540000000, 480000000, 400000000, 300000000 };

static const u32 npu7581_base[] = { 800000000, 750000000, 720000000, 600000000 };

static const u32 crypto_base[] = { 540000000, 480000000 };



static const struct en_clk_desc en7523_base_clks[] = {

	{
@@ -186,6 +191,102 @@ static const struct en_clk_desc en7523_base_clks[] = { 
	}

};



static const struct en_clk_desc en7581_base_clks[] = {

	{

		.id = EN7523_CLK_GSW,

		.name = "gsw",



		.base_reg = REG_GSW_CLK_DIV_SEL,

		.base_bits = 1,

		.base_shift = 8,

		.base_values = gsw_base,

		.n_base_values = ARRAY_SIZE(gsw_base),



		.div_bits = 3,

		.div_shift = 0,

		.div_step = 1,

		.div_offset = 1,

	}, {

		.id = EN7523_CLK_EMI,

		.name = "emi",



		.base_reg = REG_EMI_CLK_DIV_SEL,

		.base_bits = 2,

		.base_shift = 8,

		.base_values = emi7581_base,

		.n_base_values = ARRAY_SIZE(emi7581_base),



		.div_bits = 3,

		.div_shift = 0,

		.div_step = 1,

		.div_offset = 1,

	}, {

		.id = EN7523_CLK_BUS,

		.name = "bus",



		.base_reg = REG_BUS_CLK_DIV_SEL,

		.base_bits = 1,

		.base_shift = 8,

		.base_values = bus_base,

		.n_base_values = ARRAY_SIZE(bus_base),



		.div_bits = 3,

		.div_shift = 0,

		.div_step = 1,

		.div_offset = 1,

	}, {

		.id = EN7523_CLK_SLIC,

		.name = "slic",



		.base_reg = REG_SPI_CLK_FREQ_SEL,

		.base_bits = 1,

		.base_shift = 0,

		.base_values = slic_base,

		.n_base_values = ARRAY_SIZE(slic_base),



		.div_reg = REG_SPI_CLK_DIV_SEL,

		.div_bits = 5,

		.div_shift = 24,

		.div_val0 = 20,

		.div_step = 2,

	}, {

		.id = EN7523_CLK_SPI,

		.name = "spi",



		.base_reg = REG_SPI_CLK_DIV_SEL,



		.base_value = 400000000,



		.div_bits = 5,

		.div_shift = 8,

		.div_val0 = 40,

		.div_step = 2,

	}, {

		.id = EN7523_CLK_NPU,

		.name = "npu",



		.base_reg = REG_NPU_CLK_DIV_SEL,

		.base_bits = 2,

		.base_shift = 8,

		.base_values = npu7581_base,

		.n_base_values = ARRAY_SIZE(npu7581_base),



		.div_bits = 3,

		.div_shift = 0,

		.div_step = 1,

		.div_offset = 1,

	}, {

		.id = EN7523_CLK_CRYPTO,

		.name = "crypto",



		.base_reg = REG_CRYPTO_CLKSRC2,

		.base_bits = 1,

		.base_shift = 0,

		.base_values = crypto_base,

		.n_base_values = ARRAY_SIZE(crypto_base),

	}

};



static const u16 en7581_rst_ofs[] = {

	REG_RST_CTRL2,

	REG_RST_CTRL1,
@@ -457,8 +558,8 @@ static void en7581_register_clocks(struct device *dev, struct clk_hw_onecell_dat 
	u32 rate;

	int i;



	for (i = 0; i < ARRAY_SIZE(en7523_base_clks); i++) {

		const struct en_clk_desc *desc = &en7523_base_clks[i];

	for (i = 0; i < ARRAY_SIZE(en7581_base_clks); i++) {

		const struct en_clk_desc *desc = &en7581_base_clks[i];

		u32 val, reg = desc->div_reg ? desc->div_reg : desc->base_reg;

		int err;