Commit fabf0562 authored by Joey Gouly's avatar Joey Gouly Committed by Will Deacon
Browse files

kselftest/arm64: add HWCAP test for FEAT_S1POE 



Check that when POE is enabled, the POR_EL0 register is accessible.

Signed-off-by: default avatarJoey Gouly <joey.gouly@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Mark Brown <broonie@kernel.org>
Cc: Shuah Khan <shuah@kernel.org>
Reviewed-by: default avatarMark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20240822151113.1479789-28-joey.gouly@arm.com


Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent f5b5ea51

tools/testing/selftests/arm64/abi/hwcap.c

+14 −0
Original line number Diff line number Diff line
@@ -156,6 +156,12 @@ static void pmull_sigill(void) 
	asm volatile(".inst 0x0ee0e000" : : : );

}



static void poe_sigill(void)

{

	/* mrs x0, POR_EL0 */

	asm volatile("mrs x0, S3_3_C10_C2_4" : : : "x0");

}



static void rng_sigill(void)

{

	asm volatile("mrs x0, S3_3_C2_C4_0" : : : "x0");
@@ -601,6 +607,14 @@ static const struct hwcap_data { 
		.cpuinfo = "pmull",

		.sigill_fn = pmull_sigill,

	},

	{

		.name = "POE",

		.at_hwcap = AT_HWCAP2,

		.hwcap_bit = HWCAP2_POE,

		.cpuinfo = "poe",

		.sigill_fn = poe_sigill,

		.sigill_reliable = true,

	},

	{

		.name = "RNG",

		.at_hwcap = AT_HWCAP2,