Commit fad3dad8 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-next-2024-04-17-1' of... 

Merge tag 'drm-intel-next-2024-04-17-1' of https://anongit.freedesktop.org/git/drm/drm-intel

 into drm-next

Core Changes (DRM):

- Fix documentation of DP tunnel functions (Imre)
- DP MST read sideband messaging cap (Jani)
- Preparation patches for Adaptive Sync SDP Support for DP (Mitul)

Driver Changes:

i915 core (non-display):
- Documentation improvements (Nirmoy)
- Add includes for BUG_ON/BUILD_BUG_ON in i915_memcpy.c (Joonas)
- Do not print 'pxp init failed with 0' when it succeed (Jose)
- Clean-up, including removal of dead code for unsupported platforms (Lucas)
- Adding new DG2 PCI ID (Ravi)

{i915,xe} display:
- Spelling fix (Colin Ian)
- Document CDCLK components (Gustavo)
- Lunar Lake display enabling, including cdclk and other refactors (Gustavo, Bala)
- BIOS/VBT/opregion related refactor (Jani, Ville, RK)
- Save a few bytes of memory using {kstrdup,kfree}_const variant (Christophe)
- Digital port related refactor/clean-up (Ville)
- Fix 2s boot time regression on DP panel replay init (Animesh)
- Remove redundant drm_rect_visible() overlay use (Arthur)
- DSC HW state readout fixes (Imre)
- Remove duplication on audio enable/disable on SDVO and g4x+ DP (Ville)
- Disable AuxCCS framebuffers if built for Xe (Juha-Pekka)
- Fix DSI init order (Ville)
- DRRS related refactor and fixes (Bhanuprakash)
- Fix DSB vblank waits with VRR (Ville)
- General improvements on register name and use of REG_BIT (Ville)
- Some display power well related improvements (Ville)
- FBC changes for better w/a handling (Ville)
- Make crtc disable more atomic (Ville)
- Fix hwmon locking inversion in sysfs getter (Janusz)
- Increase DP idle pattern wait timeout to 2ms (Shekhar)
- PSR related fixes and improvents (Jouni)
- Start using container_of_const() for some extra const safety (Ville)
- Use drm_printer more on display code (Ville)
- Fix Jasper Lake boot freeze (Jonathon)
- Update Pipe src size check in skl_update_scaler (Ankit)
- Enable MST mode for 128b/132b single-stream sideband (Jani)
- Pass encoder around more for port/phy checks (Jani)
- Some initial work to make display code more independent from i915 (Jani)
- Pre-populate the cursor physical dma address (Ville)
- Do not bump min backlight brightness to max on enable (Gareth)
- Fix MTL supported DP rates - removal of UHBR13.5 (Arun)
- Fix the computation for compressed_bpp for DISPLAY < 1 (Ankit)
- Bigjoiner modeset sequence redesign and MST support (Ville)
- Enable Adaptive Sync SDP Support for DP (Mitul)
- Implemnt vblank sycnhronized mbus joining changes (Ville, Stanislav)
- HDCP related fixes (Suraj)
- Fix i915_display_info debugfs when connectors are not active (Ville)
- Clean up on Xe compat layer (Jani)
- Add jitter WAs for MST/FEC/DSC links (Imre)
- DMC wakelock implementation (Luca)

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

# -----BEGIN PGP SIGNATURE-----
#
# iQEzBAABCAAdFiEEbSBwaO7dZQkcLOKj+mJfZA7rE8oFAmYfzQEACgkQ+mJfZA7r
# E8qYvAf/T8KrEewHOWz7NOaKcFRCNYaF4QTdVOfgHUYBX5NPDF/xzwFdHCL8QWQu
# bwKwE2b94VEyruG3DYwTMd8GNcDxrsOrmU0IZe3PVkm+BvHLTmrOqL6BlCd85zXF
# 02IuE+LCaWREmmpLMcsDMxsaaq8yp+cw9/F0jJDrH6LiyfxFriefxyZYpGYjRCuv
# 8GP1fHXLFV2yys4rveR/+y9xIhgy82mVcg3/Kfk0+er7gALkY6Vc0N38wedET9MZ
# ZPfVidBeaTkIKcCDFKnFzGjG+9rNQ7NFrXyS7Hl97VolGt2l03qGGPNW1PouDiUx
# 7Y8CJOc+1k9wyBMKl0a/NQBRAqSZBQ==
# =JvZN
# -----END PGP SIGNATURE-----
# gpg: Signature made Wed 17 Apr 2024 23:22:09 AEST
# gpg:                using RSA key 6D207068EEDD65091C2CE2A3FA625F640EEB13CA
# gpg: Good signature from "Rodrigo Vivi <rodrigo.vivi@intel.com>" [unknown]
# gpg:                 aka "Rodrigo Vivi <rodrigo.vivi@gmail.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6D20 7068 EEDD 6509 1C2C  E2A3 FA62 5F64 0EEB 13CA
From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/Zh_Q72gYKMMbge9A@intel.com
parents 34633158 700c3401

Documentation/gpu/i915.rst

+9 −0
Original line number Diff line number Diff line
@@ -204,6 +204,15 @@ DMC Firmware Support 
.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dmc.c

   :internal:



DMC wakelock support

--------------------



.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dmc_wl.c

   :doc: DMC wakelock support



.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dmc_wl.c

   :internal:



Video BIOS Table (VBT)

----------------------

Documentation/gpu/rfc/i915_vm_bind.h

+5 −6
Original line number Diff line number Diff line
@@ -93,12 +93,11 @@ struct drm_i915_gem_timeline_fence { 
 * Multiple VA mappings can be created to the same section of the object

 * (aliasing).

 *

 * The @start, @offset and @length must be 4K page aligned. However the DG2

 * and XEHPSDV has 64K page size for device local memory and has compact page

 * table. On those platforms, for binding device local-memory objects, the

 * @start, @offset and @length must be 64K aligned. Also, UMDs should not mix

 * the local memory 64K page and the system memory 4K page bindings in the same

 * 2M range.

 * The @start, @offset and @length must be 4K page aligned. However the DG2 has

 * 64K page size for device local memory and has compact page table. On that

 * platform, for binding device local-memory objects, the @start, @offset and

 * @length must be 64K aligned. Also, UMDs should not mix the local memory 64K

 * page and the system memory 4K page bindings in the same 2M range.

 *

 * Error code -EINVAL will be returned if @start, @offset and @length are not

 * properly aligned. In version 1 (See I915_PARAM_VM_BIND_VERSION), error code

drivers/gpu/drm/display/drm_dp_helper.c

+37 −0
Original line number Diff line number Diff line
@@ -2948,6 +2948,43 @@ void drm_dp_vsc_sdp_log(struct drm_printer *p, const struct drm_dp_vsc_sdp *vsc) 
}

EXPORT_SYMBOL(drm_dp_vsc_sdp_log);



void drm_dp_as_sdp_log(struct drm_printer *p, const struct drm_dp_as_sdp *as_sdp)

{

	drm_printf(p, "DP SDP: AS_SDP, revision %u, length %u\n",

		   as_sdp->revision, as_sdp->length);

	drm_printf(p, "    vtotal: %d\n", as_sdp->vtotal);

	drm_printf(p, "    target_rr: %d\n", as_sdp->target_rr);

	drm_printf(p, "    duration_incr_ms: %d\n", as_sdp->duration_incr_ms);

	drm_printf(p, "    duration_decr_ms: %d\n", as_sdp->duration_decr_ms);

	drm_printf(p, "    operation_mode: %d\n", as_sdp->mode);

}

EXPORT_SYMBOL(drm_dp_as_sdp_log);



/**

 * drm_dp_as_sdp_supported() - check if adaptive sync sdp is supported

 * @aux: DisplayPort AUX channel

 * @dpcd: DisplayPort configuration data

 *

 * Returns true if adaptive sync sdp is supported, else returns false

 */

bool drm_dp_as_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE])

{

	u8 rx_feature;



	if (dpcd[DP_DPCD_REV] < DP_DPCD_REV_13)

		return false;



	if (drm_dp_dpcd_readb(aux, DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1,

			      &rx_feature) != 1) {

		drm_dbg_dp(aux->drm_dev,

			   "Failed to read DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1\n");

		return false;

	}



	return (rx_feature & DP_ADAPTIVE_SYNC_SDP_SUPPORTED);

}

EXPORT_SYMBOL(drm_dp_as_sdp_supported);



/**

 * drm_dp_vsc_sdp_supported() - check if vsc sdp is supported

 * @aux: DisplayPort AUX channel

drivers/gpu/drm/display/drm_dp_mst_topology.c

+13 −7
Original line number Diff line number Diff line
@@ -3608,24 +3608,30 @@ fixed20_12 drm_dp_get_vc_payload_bw(const struct drm_dp_mst_topology_mgr *mgr, 
EXPORT_SYMBOL(drm_dp_get_vc_payload_bw);



/**

 * drm_dp_read_mst_cap() - check whether or not a sink supports MST

 * drm_dp_read_mst_cap() - Read the sink's MST mode capability

 * @aux: The DP AUX channel to use

 * @dpcd: A cached copy of the DPCD capabilities for this sink

 *

 * Returns: %True if the sink supports MST, %false otherwise

 * Returns: enum drm_dp_mst_mode to indicate MST mode capability

 */

bool drm_dp_read_mst_cap(struct drm_dp_aux *aux,

enum drm_dp_mst_mode drm_dp_read_mst_cap(struct drm_dp_aux *aux,

					 const u8 dpcd[DP_RECEIVER_CAP_SIZE])

{

	u8 mstm_cap;



	if (dpcd[DP_DPCD_REV] < DP_DPCD_REV_12)

		return false;

		return DRM_DP_SST;



	if (drm_dp_dpcd_readb(aux, DP_MSTM_CAP, &mstm_cap) != 1)

		return false;

		return DRM_DP_SST;



	if (mstm_cap & DP_MST_CAP)

		return DRM_DP_MST;



	if (mstm_cap & DP_SINGLE_STREAM_SIDEBAND_MSG)

		return DRM_DP_SST_SIDEBAND_MSG;



	return mstm_cap & DP_MST_CAP;

	return DRM_DP_SST;

}

EXPORT_SYMBOL(drm_dp_read_mst_cap);

drivers/gpu/drm/display/drm_dp_tunnel.c

+4 −3
Original line number Diff line number Diff line
@@ -436,8 +436,8 @@ EXPORT_SYMBOL(drm_dp_tunnel_get); 


/**

 * drm_dp_tunnel_put - Put a reference for a DP tunnel

 * @tunnel - Tunnel object

 * @tracker - Debug tracker for the reference

 * @tunnel: Tunnel object

 * @tracker: Debug tracker for the reference

 *

 * Put a reference for @tunnel along with its debug *@tracker, which

 * was obtained with drm_dp_tunnel_get().
@@ -1170,7 +1170,7 @@ int drm_dp_tunnel_alloc_bw(struct drm_dp_tunnel *tunnel, int bw) 
EXPORT_SYMBOL(drm_dp_tunnel_alloc_bw);



/**

 * drm_dp_tunnel_atomic_get_allocated_bw - Get the BW allocated for a DP tunnel

 * drm_dp_tunnel_get_allocated_bw - Get the BW allocated for a DP tunnel

 * @tunnel: Tunnel object

 *

 * Get the current BW allocated for @tunnel. After the tunnel is created /
@@ -1892,6 +1892,7 @@ static void destroy_mgr(struct drm_dp_tunnel_mgr *mgr) 
/**

 * drm_dp_tunnel_mgr_create - Create a DP tunnel manager

 * @dev: DRM device object

 * @max_group_count: Maximum number of tunnel groups

 *

 * Creates a DP tunnel manager for @dev.

 *