Commit faf51b20 authored by Fangzhi Zuo's avatar Fangzhi Zuo Committed by Alex Deucher
Browse files

drm/amd/display: Fix dcn35 8k30 Underflow/Corruption Issue 



[why]
odm calculation is missing for pipe split policy determination
and cause Underflow/Corruption issue.

[how]
Add the odm calculation.

Cc: Mario Limonciello <mario.limonciello@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Reviewed-by: default avatarCharlene Liu <charlene.liu@amd.com>
Acked-by: default avatarTom Chung <chiahsuan.chung@amd.com>
Signed-off-by: default avatarFangzhi Zuo <jerry.zuo@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 191cb4ed

drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c

+11 −18
Original line number Diff line number Diff line
@@ -791,35 +791,28 @@ static void populate_dml_surface_cfg_from_plane_state(enum dml_project_id dml2_p 
	}

}



/*TODO no support for mpc combine, need rework - should calculate scaling params based on plane+stream*/

static struct scaler_data get_scaler_data_for_plane(const struct dc_plane_state *in, const struct dc_state *context)

static struct scaler_data get_scaler_data_for_plane(const struct dc_plane_state *in, struct dc_state *context)

{

	int i;

	struct scaler_data data = { 0 };

	struct pipe_ctx *temp_pipe = &context->res_ctx.temp_pipe;



	memset(temp_pipe, 0, sizeof(struct pipe_ctx));



	for (i = 0; i < MAX_PIPES; i++)	{

		const struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];



		if (pipe->plane_state == in && !pipe->prev_odm_pipe) {

			const struct pipe_ctx *next_pipe = pipe->next_odm_pipe;



			data = context->res_ctx.pipe_ctx[i].plane_res.scl_data;

			while (next_pipe) {

				data.h_active += next_pipe->plane_res.scl_data.h_active;

				data.recout.width += next_pipe->plane_res.scl_data.recout.width;

				if (in->rotation == ROTATION_ANGLE_0 || in->rotation == ROTATION_ANGLE_180) {

					data.viewport.width += next_pipe->plane_res.scl_data.viewport.width;

				} else {

					data.viewport.height += next_pipe->plane_res.scl_data.viewport.height;

				}

				next_pipe = next_pipe->next_odm_pipe;

			}

			temp_pipe->stream = pipe->stream;

			temp_pipe->plane_state = pipe->plane_state;

			temp_pipe->plane_res.scl_data.taps = pipe->plane_res.scl_data.taps;



			resource_build_scaling_params(temp_pipe);

			break;

		}

	}



	ASSERT(i < MAX_PIPES);

	return data;

	return temp_pipe->plane_res.scl_data;

}



static void populate_dummy_dml_plane_cfg(struct dml_plane_cfg_st *out, unsigned int location, const struct dc_stream_state *in)
@@ -864,7 +857,7 @@ static void populate_dummy_dml_plane_cfg(struct dml_plane_cfg_st *out, unsigned 
	out->ScalerEnabled[location] = false;

}



static void populate_dml_plane_cfg_from_plane_state(struct dml_plane_cfg_st *out, unsigned int location, const struct dc_plane_state *in, const struct dc_state *context)

static void populate_dml_plane_cfg_from_plane_state(struct dml_plane_cfg_st *out, unsigned int location, const struct dc_plane_state *in, struct dc_state *context)

{

	const struct scaler_data scaler_data = get_scaler_data_for_plane(in, context);

drivers/gpu/drm/amd/display/dc/inc/core_types.h

+2 −0
Original line number Diff line number Diff line
@@ -469,6 +469,8 @@ struct resource_context { 
	unsigned int hpo_dp_link_enc_to_link_idx[MAX_HPO_DP2_LINK_ENCODERS];

	int hpo_dp_link_enc_ref_cnts[MAX_HPO_DP2_LINK_ENCODERS];

	bool is_mpc_3dlut_acquired[MAX_PIPES];

	/* solely used for build scalar data in dml2 */

	struct pipe_ctx temp_pipe;

};



struct dce_bw_output {