Commit fb912a1b authored by Nikita Yushchenko's avatar Nikita Yushchenko Committed by Geert Uytterhoeven
Browse files

arm64: dts: renesas: rcar-gen3: Add MOST devices 



This patch adds the MLP device nodes to dtsi files for R-Car Gen3 SoCs
that have it.

Signed-off-by: default avatarNikita Yushchenko <nikita.yoush@cogentembedded.com>
Link: https://lore.kernel.org/r/20220120051559.746322-1-nikita.yoush@cogentembedded.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 953b392a

arch/arm64/boot/dts/renesas/r8a77951.dtsi

+12 −0
Original line number Diff line number Diff line
@@ -2412,6 +2412,18 @@ ssi9: ssi-9 { 
			};

		};



		mlp: mlp@ec520000 {

			compatible = "renesas,r8a7795-mlp",

				     "renesas,rcar-gen3-mlp";

			reg = <0 0xec520000 0 0x800>;

			interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 802>;

			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;

			resets = <&cpg 802>;

			status = "disabled";

		};



		audma0: dma-controller@ec700000 {

			compatible = "renesas,dmac-r8a7795",

				     "renesas,rcar-dmac";

arch/arm64/boot/dts/renesas/r8a77960.dtsi

+12 −0
Original line number Diff line number Diff line
@@ -2284,6 +2284,18 @@ ssiu97: ssiu-51 { 
			};

		};



		mlp: mlp@ec520000 {

			compatible = "renesas,r8a7796-mlp",

				     "renesas,rcar-gen3-mlp";

			reg = <0 0xec520000 0 0x800>;

			interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 802>;

			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;

			resets = <&cpg 802>;

			status = "disabled";

		};



		audma0: dma-controller@ec700000 {

			compatible = "renesas,dmac-r8a7796",

				     "renesas,rcar-dmac";

arch/arm64/boot/dts/renesas/r8a77961.dtsi

+12 −0
Original line number Diff line number Diff line
@@ -2128,6 +2128,18 @@ ssiu97: ssiu-51 { 
			};

		};



		mlp: mlp@ec520000 {

			compatible = "renesas,r8a77961-mlp",

				     "renesas,rcar-gen3-mlp";

			reg = <0 0xec520000 0 0x800>;

			interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 802>;

			power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;

			resets = <&cpg 802>;

			status = "disabled";

		};



		audma0: dma-controller@ec700000 {

			compatible = "renesas,dmac-r8a77961",

				     "renesas,rcar-dmac";

arch/arm64/boot/dts/renesas/r8a77965.dtsi

+12 −0
Original line number Diff line number Diff line
@@ -2147,6 +2147,18 @@ ssi9: ssi-9 { 
			};

		};



		mlp: mlp@ec520000 {

			compatible = "renesas,r8a77965-mlp",

				     "renesas,rcar-gen3-mlp";

			reg = <0 0xec520000 0 0x800>;

			interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 802>;

			power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;

			resets = <&cpg 802>;

			status = "disabled";

		};



		audma0: dma-controller@ec700000 {

			compatible = "renesas,dmac-r8a77965",

				     "renesas,rcar-dmac";

arch/arm64/boot/dts/renesas/r8a77990.dtsi

+12 −0
Original line number Diff line number Diff line
@@ -1682,6 +1682,18 @@ ssi9: ssi-9 { 
			};

		};



		mlp: mlp@ec520000 {

			compatible = "renesas,r8a77990-mlp",

				     "renesas,rcar-gen3-mlp";

			reg = <0 0xec520000 0 0x800>;

			interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 802>;

			power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;

			resets = <&cpg 802>;

			status = "disabled";

		};



		audma0: dma-controller@ec700000 {

			compatible = "renesas,dmac-r8a77990",

				     "renesas,rcar-dmac";