Commit fbb86b0d authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'phy-for-6.12' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy 

Pull phy updates from Vinod Koul:
 "New hw support:
   - Rcar usb2 support for RZ/G3S SoC
   - Nuvoton MA35 SoC USB 2.0 PHY driver

  Removed:
   - obsolete qcom,usb-8x16-phy bindings

  Updates:
   - 4 lane PCIe support for Qualcomm X1E80100
   - Constify structure in subsystem update
   - Subsystem simplification with scoped for each OF child loop update
   - Yaml conversion for Qualcomm sata phy, Hiilicon hi3798cv200-combphy
     bindings"

* tag 'phy-for-6.12' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (40 commits)
  phy: renesas: rcar-gen3-usb2: Add support for the RZ/G3S SoC
  dt-bindings: phy: renesas,usb2-phy: Document RZ/G3S phy bindings
  phy: renesas: rcar-gen3-usb2: Add support to initialize the bus
  phy: ti: j721e-wiz: Simplify with scoped for each OF child loop
  phy: ti: j721e-wiz: Drop OF node reference earlier for simpler code
  phy: ti: gmii-sel: Simplify with dev_err_probe()
  phy: ti: am654-serdes: Use scoped device node handling to simplify error paths
  phy: qcom: qmp-pcie-msm8996: Simplify with scoped for each OF child loop
  phy: mediatek: xsphy: Simplify with scoped for each OF child loop
  phy: mediatek: tphy: Simplify with scoped for each OF child loop
  phy: hisilicon: usb2: Simplify with scoped for each OF child loop
  phy: cadence: sierra: Simplify with scoped for each OF child loop
  phy: broadcom: brcm-sata: Simplify with scoped for each OF child loop
  phy: broadcom: bcm-cygnus-pcie: Simplify with scoped for each OF child loop
  phy: nuvoton: add new driver for the Nuvoton MA35 SoC USB 2.0 PHY
  dt-bindings: phy: nuvoton,ma35-usb2-phy: add new bindings
  phy: qcom: qmp-pcie: Configure all tables on port B PHY
  phy: airoha: adjust initialization delay in airoha_pcie_phy_init()
  dt-bindings: phy: socionext,uniphier: add top-level constraints
  phy: qcom: qmp-pcie: Add Gen4 4-lanes mode for X1E80100
  ...
parents 7116747a 3c2ea12a

Documentation/devicetree/bindings/phy/hisilicon,hi3798cv200-combphy.yaml

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# SPDX-License-Identifier: GPL-2.0

%YAML 1.2

---

$id: http://devicetree.org/schemas/phy/hisilicon,hi3798cv200-combphy.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: HiSilicon STB PCIE/SATA/USB3 PHY



maintainers:

  - Shawn Guo <shawn.guo@linaro.org>



properties:

  compatible:

    const: hisilicon,hi3798cv200-combphy



  reg:

    maxItems: 1



  '#phy-cells':

    description: The cell contains the PHY mode

    const: 1



  clocks:

    maxItems: 1



  resets:

    maxItems: 1



  hisilicon,fixed-mode:

    description: If the phy device doesn't support mode select but a fixed mode

      setting, the property should be present to specify the particular mode.

    $ref: /schemas/types.yaml#/definitions/uint32

    enum: [ 1, 2, 4]  # SATA, PCIE, USB3



  hisilicon,mode-select-bits:

    description: If the phy device support mode select, this property should be

      present to specify the register bits in peripheral controller.

    items:

      - description: register_offset

      - description: bit shift

      - description: bit mask



required:

  - compatible

  - reg

  - '#phy-cells'

  - clocks

  - resets



oneOf:

  - required: ['hisilicon,fixed-mode']

  - required: ['hisilicon,mode-select-bits']



additionalProperties: false



...

Documentation/devicetree/bindings/phy/nuvoton,ma35d1-usb2-phy.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/phy/nuvoton,ma35d1-usb2-phy.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Nuvoton MA35D1 USB2 phy



maintainers:

  - Hui-Ping Chen <hpchen0nvt@gmail.com>



properties:

  compatible:

    enum:

      - nuvoton,ma35d1-usb2-phy



  "#phy-cells":

    const: 0



  clocks:

    maxItems: 1



  nuvoton,sys:

    $ref: /schemas/types.yaml#/definitions/phandle

    description:

      phandle to syscon for checking the PHY clock status.



required:

  - compatible

  - "#phy-cells"

  - clocks

  - nuvoton,sys



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/nuvoton,ma35d1-clk.h>



    usb_phy: usb-phy {

        compatible = "nuvoton,ma35d1-usb2-phy";

        clocks = <&clk USBD_GATE>;

        nuvoton,sys = <&sys>;

        #phy-cells = <0>;

    };

Documentation/devicetree/bindings/phy/phy-hi3798cv200-combphy.txt

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HiSilicon STB PCIE/SATA/USB3 PHY



Required properties:

- compatible: Should be "hisilicon,hi3798cv200-combphy"

- reg: Should be the address space for COMBPHY configuration and state

  registers in peripheral controller, e.g. PERI_COMBPHY0_CFG and

  PERI_COMBPHY0_STATE for COMBPHY0 Hi3798CV200 SoC.

- #phy-cells: Should be 1.  The cell number is used to select the phy mode

  as defined in <dt-bindings/phy/phy.h>.

- clocks: The phandle to clock provider and clock specifier pair.

- resets: The phandle to reset controller and reset specifier pair.



Refer to phy/phy-bindings.txt for the generic PHY binding properties.



Optional properties:

- hisilicon,fixed-mode: If the phy device doesn't support mode select

  but a fixed mode setting, the property should be present to specify

  the particular mode.

- hisilicon,mode-select-bits: If the phy device support mode select,

  this property should be present to specify the register bits in

  peripheral controller, as a 3 integers tuple:

  <register_offset bit_shift bit_mask>.



Notes:

- Between hisilicon,fixed-mode and hisilicon,mode-select-bits, one and only

  one of them should be present.

- The device node should be a child of peripheral controller that contains

  COMBPHY configuration/state and PERI_CTRL register used to select PHY mode.

  Refer to arm/hisilicon/hisilicon.txt for the parent peripheral controller

  bindings.



Examples:



perictrl: peripheral-controller@8a20000 {

	compatible = "hisilicon,hi3798cv200-perictrl", "syscon",

		     "simple-mfd";

	reg = <0x8a20000 0x1000>;

	#address-cells = <1>;

	#size-cells = <1>;

	ranges = <0x0 0x8a20000 0x1000>;



	combphy0: phy@850 {

		compatible = "hisilicon,hi3798cv200-combphy";

		reg = <0x850 0x8>;

		#phy-cells = <1>;

		clocks = <&crg HISTB_COMBPHY0_CLK>;

		resets = <&crg 0x188 4>;

		hisilicon,fixed-mode = <PHY_TYPE_USB3>;

	};



	combphy1: phy@858 {

		compatible = "hisilicon,hi3798cv200-combphy";

		reg = <0x858 0x8>;

		#phy-cells = <1>;

		clocks = <&crg HISTB_COMBPHY1_CLK>;

		resets = <&crg 0x188 12>;

		hisilicon,mode-select-bits = <0x0008 11 (0x3 << 11)>;

	};

};

Documentation/devicetree/bindings/phy/qcom,sata-phy.yaml

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/phy/qcom,sata-phy.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm SATA PHY Controller



maintainers:

  - Bjorn Andersson <andersson@kernel.org>

  - Konrad Dybcio <konrad.dybcio@linaro.org>



description:

  The Qualcomm SATA PHY describes on-chip SATA Physical layer controllers.



properties:

  compatible:

    enum:

      - qcom,ipq806x-sata-phy

      - qcom,apq8064-sata-phy



  reg:

    maxItems: 1



  clocks:

    maxItems: 1



  clock-names:

    const: cfg



  '#phy-cells':

    const: 0



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - '#phy-cells'



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/qcom,gcc-ipq806x.h>

    sata_phy: sata-phy@1b400000 {

        compatible = "qcom,ipq806x-sata-phy";

        reg = <0x1b400000 0x200>;



        clocks = <&gcc SATA_PHY_CFG_CLK>;

        clock-names = "cfg";



        #phy-cells = <0>;

    };

Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml

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@@ -40,6 +40,7 @@ properties: 
      - qcom,sm8650-qmp-gen4x2-pcie-phy

      - qcom,x1e80100-qmp-gen3x2-pcie-phy

      - qcom,x1e80100-qmp-gen4x2-pcie-phy

      - qcom,x1e80100-qmp-gen4x4-pcie-phy



  reg:

    minItems: 1
@@ -118,6 +119,7 @@ allOf: 
          contains:

            enum:

              - qcom,sc8280xp-qmp-gen3x4-pcie-phy

              - qcom,x1e80100-qmp-gen4x4-pcie-phy

    then:

      properties:

        reg:
@@ -169,6 +171,7 @@ allOf: 
              - qcom,sc8280xp-qmp-gen3x1-pcie-phy

              - qcom,sc8280xp-qmp-gen3x2-pcie-phy

              - qcom,sc8280xp-qmp-gen3x4-pcie-phy

              - qcom,x1e80100-qmp-gen4x4-pcie-phy

    then:

      properties:

        clocks: