Commit fbf937a8 authored by Li Liu's avatar Li Liu Committed by Dmitry Baryshkov
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drm/msm/dsi: Add dsi phy support for SM6150 



Add phy configuration for SM6150

Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: default avatarLi Liu <quic_lliu6@quicinc.com>
Signed-off-by: default avatarFange Zhang <quic_fangez@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/628009/
Link: https://lore.kernel.org/r/20241210-add-display-support-for-qcs615-platform-v4-6-2d875a67602d@quicinc.com


Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
parent cb2f9144

drivers/gpu/drm/msm/dsi/phy/dsi_phy.c

+2 −0
Original line number Diff line number Diff line
@@ -567,6 +567,8 @@ static const struct of_device_id dsi_phy_dt_match[] = { 
	  .data = &dsi_phy_14nm_8953_cfgs },

	{ .compatible = "qcom,sm6125-dsi-phy-14nm",

	  .data = &dsi_phy_14nm_2290_cfgs },

	{ .compatible = "qcom,sm6150-dsi-phy-14nm",

	  .data = &dsi_phy_14nm_6150_cfgs },

#endif

#ifdef CONFIG_DRM_MSM_DSI_10NM_PHY

	{ .compatible = "qcom,dsi-phy-10nm",

drivers/gpu/drm/msm/dsi/phy/dsi_phy.h

+1 −0
Original line number Diff line number Diff line
@@ -46,6 +46,7 @@ extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8937_cfgs; 
extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs;

extern const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs;

extern const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs;

extern const struct msm_dsi_phy_cfg dsi_phy_14nm_6150_cfgs;

extern const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs;

extern const struct msm_dsi_phy_cfg dsi_phy_14nm_2290_cfgs;

extern const struct msm_dsi_phy_cfg dsi_phy_14nm_8953_cfgs;

drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c

+21 −0
Original line number Diff line number Diff line
@@ -1032,6 +1032,10 @@ static const struct regulator_bulk_data dsi_phy_14nm_73p4mA_regulators[] = { 
	{ .supply = "vcca", .init_load_uA = 73400 },

};



static const struct regulator_bulk_data dsi_phy_14nm_36mA_regulators[] = {

	{ .supply = "vdda", .init_load_uA = 36000 },

};



const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs = {

	.has_phy_lane = true,

	.regulator_data = dsi_phy_14nm_17mA_regulators,
@@ -1097,3 +1101,20 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_2290_cfgs = { 
	.io_start = { 0x5e94400 },

	.num_dsi_phy = 1,

};



const struct msm_dsi_phy_cfg dsi_phy_14nm_6150_cfgs = {

	.has_phy_lane = true,

	.regulator_data = dsi_phy_14nm_36mA_regulators,

	.num_regulators = ARRAY_SIZE(dsi_phy_14nm_36mA_regulators),

	.ops = {

		.enable = dsi_14nm_phy_enable,

		.disable = dsi_14nm_phy_disable,

		.pll_init = dsi_pll_14nm_init,

		.save_pll_state = dsi_14nm_pll_save_state,

		.restore_pll_state = dsi_14nm_pll_restore_state,

	},

	.min_pll_rate = VCO_MIN_RATE,

	.max_pll_rate = VCO_MAX_RATE,

	.io_start = { 0xae94400 },

	.num_dsi_phy = 1,

};