Commit fbf97d6c authored by Ariel D'Alessandro's avatar Ariel D'Alessandro Committed by Rob Herring (Arm)
Browse files

dt-bindings: media: Convert MediaTek mt8173-mdp bindings to DT schema 



Convert the existing text-based DT bindings for MediaTek MT8173 Media Data
Path to a DT schema.

Signed-off-by: default avatarAriel D'Alessandro <ariel.dalessandro@collabora.com>
Reviewed-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://patch.msgid.link/20251001183115.83111-1-ariel.dalessandro@collabora.com


Signed-off-by: default avatarRob Herring (Arm) <robh@kernel.org>
parent fc751092

Documentation/devicetree/bindings/media/mediatek,mt8173-mdp.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/media/mediatek,mt8173-mdp.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: MediaTek MT8173 Media Data Path



maintainers:

  - Ariel D'Alessandro <ariel.dalessandro@collabora.com>



description:

  Media Data Path is used for scaling and color space conversion.



properties:

  compatible:

    oneOf:

      - enum:

          - mediatek,mt8173-mdp-rdma

          - mediatek,mt8173-mdp-rsz

          - mediatek,mt8173-mdp-wdma

          - mediatek,mt8173-mdp-wrot

      - items:

          - const: mediatek,mt8173-mdp-rdma

          - const: mediatek,mt8173-mdp



  reg:

    maxItems: 1



  clocks:

    minItems: 1

    maxItems: 2



  power-domains:

    maxItems: 1



  iommus:

    maxItems: 1



  mediatek,vpu:

    $ref: /schemas/types.yaml#/definitions/phandle

    description:

      phandle to Mediatek Video Processor Unit for HW Codec encode/decode and

      image processing.



required:

  - compatible

  - reg

  - clocks

  - power-domains



allOf:

  - if:

      properties:

        compatible:

          contains:

            const: mediatek,mt8173-mdp-rdma

    then:

      properties:

        clocks:

          items:

            - description: Main clock

            - description: Mutex clock

    else:

      properties:

        clocks:

          items:

            - description: Main clock



  - if:

      properties:

        compatible:

          contains:

            enum:

              - mediatek,mt8173-mdp-rdma

              - mediatek,mt8173-mdp-wdma

              - mediatek,mt8173-mdp-wrot

    then:

      required:

        - iommus



  - if:

      properties:

        compatible:

          contains:

            const: mediatek,mt8173-mdp

    then:

      required:

        - mediatek,vpu



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/mt8173-clk.h>

    #include <dt-bindings/memory/mt8173-larb-port.h>

    #include <dt-bindings/power/mt8173-power.h>



    soc {

        #address-cells = <2>;

        #size-cells = <2>;



        mdp_rdma0: rdma@14001000 {

            compatible = "mediatek,mt8173-mdp-rdma",

                         "mediatek,mt8173-mdp";

            reg = <0 0x14001000 0 0x1000>;

            clocks = <&mmsys CLK_MM_MDP_RDMA0>,

                     <&mmsys CLK_MM_MUTEX_32K>;

            power-domains = <&spm MT8173_POWER_DOMAIN_MM>;

            iommus = <&iommu M4U_PORT_MDP_RDMA0>;

            mediatek,vpu = <&vpu>;

        };



        mdp_rdma1: rdma@14002000 {

            compatible = "mediatek,mt8173-mdp-rdma";

            reg = <0 0x14002000 0 0x1000>;

            clocks = <&mmsys CLK_MM_MDP_RDMA1>,

                     <&mmsys CLK_MM_MUTEX_32K>;

            power-domains = <&spm MT8173_POWER_DOMAIN_MM>;

            iommus = <&iommu M4U_PORT_MDP_RDMA1>;

        };



        mdp_rsz0: rsz@14003000 {

            compatible = "mediatek,mt8173-mdp-rsz";

            reg = <0 0x14003000 0 0x1000>;

            clocks = <&mmsys CLK_MM_MDP_RSZ0>;

            power-domains = <&spm MT8173_POWER_DOMAIN_MM>;

        };



        mdp_rsz1: rsz@14004000 {

            compatible = "mediatek,mt8173-mdp-rsz";

            reg = <0 0x14004000 0 0x1000>;

            clocks = <&mmsys CLK_MM_MDP_RSZ1>;

            power-domains = <&spm MT8173_POWER_DOMAIN_MM>;

        };



        mdp_rsz2: rsz@14005000 {

            compatible = "mediatek,mt8173-mdp-rsz";

            reg = <0 0x14005000 0 0x1000>;

            clocks = <&mmsys CLK_MM_MDP_RSZ2>;

            power-domains = <&spm MT8173_POWER_DOMAIN_MM>;

        };



        mdp_wdma0: wdma@14006000 {

            compatible = "mediatek,mt8173-mdp-wdma";

            reg = <0 0x14006000 0 0x1000>;

            clocks = <&mmsys CLK_MM_MDP_WDMA>;

            power-domains = <&spm MT8173_POWER_DOMAIN_MM>;

            iommus = <&iommu M4U_PORT_MDP_WDMA>;

        };



        mdp_wrot0: wrot@14007000 {

            compatible = "mediatek,mt8173-mdp-wrot";

            reg = <0 0x14007000 0 0x1000>;

            clocks = <&mmsys CLK_MM_MDP_WROT0>;

            power-domains = <&spm MT8173_POWER_DOMAIN_MM>;

            iommus = <&iommu M4U_PORT_MDP_WROT0>;

        };



        mdp_wrot1: wrot@14008000 {

            compatible = "mediatek,mt8173-mdp-wrot";

            reg = <0 0x14008000 0 0x1000>;

            clocks = <&mmsys CLK_MM_MDP_WROT1>;

            power-domains = <&spm MT8173_POWER_DOMAIN_MM>;

            iommus = <&iommu M4U_PORT_MDP_WROT1>;

        };

    };



...

Documentation/devicetree/bindings/media/mediatek-mdp.txt

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* Mediatek Media Data Path



Media Data Path is used for scaling and color space conversion.



Required properties (controller node):

- compatible: "mediatek,mt8173-mdp"

- mediatek,vpu: the node of video processor unit, see

  Documentation/devicetree/bindings/media/mediatek,mt8173-vpu.yaml for 

  details.



Required properties (all function blocks, child node):

- compatible: Should be one of

        "mediatek,mt8173-mdp-rdma"  - read DMA

        "mediatek,mt8173-mdp-rsz"   - resizer

        "mediatek,mt8173-mdp-wdma"  - write DMA

        "mediatek,mt8173-mdp-wrot"  - write DMA with rotation

- reg: Physical base address and length of the function block register space

- clocks: device clocks, see

  Documentation/devicetree/bindings/clock/clock-bindings.txt for details.

- power-domains: a phandle to the power domain, see

  Documentation/devicetree/bindings/power/power_domain.txt for details.



Required properties (DMA function blocks, child node):

- compatible: Should be one of

        "mediatek,mt8173-mdp-rdma"

        "mediatek,mt8173-mdp-wdma"

        "mediatek,mt8173-mdp-wrot"

- iommus: should point to the respective IOMMU block with master port as

  argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml

  for details.



Example:

	mdp_rdma0: rdma@14001000 {

		compatible = "mediatek,mt8173-mdp-rdma";

			     "mediatek,mt8173-mdp";

		reg = <0 0x14001000 0 0x1000>;

		clocks = <&mmsys CLK_MM_MDP_RDMA0>,

			 <&mmsys CLK_MM_MUTEX_32K>;

		power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;

		iommus = <&iommu M4U_PORT_MDP_RDMA0>;

		mediatek,vpu = <&vpu>;

	};



	mdp_rdma1: rdma@14002000 {

		compatible = "mediatek,mt8173-mdp-rdma";

		reg = <0 0x14002000 0 0x1000>;

		clocks = <&mmsys CLK_MM_MDP_RDMA1>,

			 <&mmsys CLK_MM_MUTEX_32K>;

		power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;

		iommus = <&iommu M4U_PORT_MDP_RDMA1>;

	};



	mdp_rsz0: rsz@14003000 {

		compatible = "mediatek,mt8173-mdp-rsz";

		reg = <0 0x14003000 0 0x1000>;

		clocks = <&mmsys CLK_MM_MDP_RSZ0>;

		power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;

	};



	mdp_rsz1: rsz@14004000 {

		compatible = "mediatek,mt8173-mdp-rsz";

		reg = <0 0x14004000 0 0x1000>;

		clocks = <&mmsys CLK_MM_MDP_RSZ1>;

		power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;

	};



	mdp_rsz2: rsz@14005000 {

		compatible = "mediatek,mt8173-mdp-rsz";

		reg = <0 0x14005000 0 0x1000>;

		clocks = <&mmsys CLK_MM_MDP_RSZ2>;

		power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;

	};



	mdp_wdma0: wdma@14006000 {

		compatible = "mediatek,mt8173-mdp-wdma";

		reg = <0 0x14006000 0 0x1000>;

		clocks = <&mmsys CLK_MM_MDP_WDMA>;

		power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;

		iommus = <&iommu M4U_PORT_MDP_WDMA>;

	};



	mdp_wrot0: wrot@14007000 {

		compatible = "mediatek,mt8173-mdp-wrot";

		reg = <0 0x14007000 0 0x1000>;

		clocks = <&mmsys CLK_MM_MDP_WROT0>;

		power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;

		iommus = <&iommu M4U_PORT_MDP_WROT0>;

	};



	mdp_wrot1: wrot@14008000 {

		compatible = "mediatek,mt8173-mdp-wrot";

		reg = <0 0x14008000 0 0x1000>;

		clocks = <&mmsys CLK_MM_MDP_WROT1>;

		power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;

		iommus = <&iommu M4U_PORT_MDP_WROT1>;

	};