Commit fc6efed2 authored by Mukul Joshi's avatar Mukul Joshi Committed by Alex Deucher
Browse files

drm/amdkfd: Update CU masking for GFX 9.4.3 



The CU mask passed from user-space will change based on
different spatial partitioning mode. As a result, update
CU masking code for GFX9.4.3 to work for all partitioning
modes.

Signed-off-by: default avatarMukul Joshi <mukul.joshi@amd.com>
Reviewed-by: default avatarFelix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 0752e66e

drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c

+22 −6
Original line number Diff line number Diff line
@@ -97,14 +97,16 @@ void free_mqd_hiq_sdma(struct mqd_manager *mm, void *mqd, 


void mqd_symmetrically_map_cu_mask(struct mqd_manager *mm,

		const uint32_t *cu_mask, uint32_t cu_mask_count,

		uint32_t *se_mask)

		uint32_t *se_mask, uint32_t inst)

{

	struct kfd_cu_info cu_info;

	uint32_t cu_per_sh[KFD_MAX_NUM_SE][KFD_MAX_NUM_SH_PER_SE] = {0};

	bool wgp_mode_req = KFD_GC_VERSION(mm->dev) >= IP_VERSION(10, 0, 0);

	uint32_t en_mask = wgp_mode_req ? 0x3 : 0x1;

	int i, se, sh, cu, cu_bitmap_sh_mul, inc = wgp_mode_req ? 2 : 1;

	int i, se, sh, cu, cu_bitmap_sh_mul, cu_inc = wgp_mode_req ? 2 : 1;

	uint32_t cu_active_per_node;

	int inc = cu_inc * NUM_XCC(mm->dev->xcc_mask);

	int xcc_inst = inst + ffs(mm->dev->xcc_mask) - 1;



	amdgpu_amdkfd_get_cu_info(mm->dev->adev, &cu_info);
@@ -143,7 +145,8 @@ void mqd_symmetrically_map_cu_mask(struct mqd_manager *mm, 
	for (se = 0; se < cu_info.num_shader_engines; se++)

		for (sh = 0; sh < cu_info.num_shader_arrays_per_engine; sh++)

			cu_per_sh[se][sh] = hweight32(

				cu_info.cu_bitmap[0][se % 4][sh + (se / 4) * cu_bitmap_sh_mul]);

				cu_info.cu_bitmap[xcc_inst][se % 4][sh + (se / 4) *

				cu_bitmap_sh_mul]);



	/* Symmetrically map cu_mask to all SEs & SHs:

	 * se_mask programs up to 2 SH in the upper and lower 16 bits.
@@ -166,20 +169,33 @@ void mqd_symmetrically_map_cu_mask(struct mqd_manager *mm, 
	 * cu_mask[0] bit8 -> se_mask[0] bit1 (SE0,SH0,CU1)

	 * ...

	 *

	 * For GFX 9.4.3, the following code only looks at a

	 * subset of the cu_mask corresponding to the inst parameter.

	 * If we have n XCCs under one GPU node

	 * cu_mask[0] bit0 -> XCC0 se_mask[0] bit0 (XCC0,SE0,SH0,CU0)

	 * cu_mask[0] bit1 -> XCC1 se_mask[0] bit0 (XCC1,SE0,SH0,CU0)

	 * ..

	 * cu_mask[0] bitn -> XCCn se_mask[0] bit0 (XCCn,SE0,SH0,CU0)

	 * cu_mask[0] bit n+1 -> XCC0 se_mask[1] bit0 (XCC0,SE1,SH0,CU0)

	 *

	 * For example, if there are 6 XCCs under 1 KFD node, this code

	 * running for each inst, will look at the bits as:

	 * inst, inst + 6, inst + 12...

	 *

	 * First ensure all CUs are disabled, then enable user specified CUs.

	 */

	for (i = 0; i < cu_info.num_shader_engines; i++)

		se_mask[i] = 0;



	i = 0;

	for (cu = 0; cu < 16; cu += inc) {

	i = inst;

	for (cu = 0; cu < 16; cu += cu_inc) {

		for (sh = 0; sh < cu_info.num_shader_arrays_per_engine; sh++) {

			for (se = 0; se < cu_info.num_shader_engines; se++) {

				if (cu_per_sh[se][sh] > cu) {

					if (cu_mask[i / 32] & (en_mask << (i % 32)))

						se_mask[se] |= en_mask << (cu + sh * 16);

					i += inc;

					if (i == cu_mask_count)

					if (i >= cu_mask_count)

						return;

				}

			}

drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h

+1 −1
Original line number Diff line number Diff line
@@ -138,7 +138,7 @@ void free_mqd_hiq_sdma(struct mqd_manager *mm, void *mqd, 


void mqd_symmetrically_map_cu_mask(struct mqd_manager *mm,

		const uint32_t *cu_mask, uint32_t cu_mask_count,

		uint32_t *se_mask);

		uint32_t *se_mask, uint32_t inst);



int kfd_hiq_load_mqd_kiq(struct mqd_manager *mm, void *mqd,

		uint32_t pipe_id, uint32_t queue_id,

drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c

+1 −1
Original line number Diff line number Diff line
@@ -52,7 +52,7 @@ static void update_cu_mask(struct mqd_manager *mm, void *mqd, 
		return;



	mqd_symmetrically_map_cu_mask(mm,

		minfo->cu_mask.ptr, minfo->cu_mask.count, se_mask);

		minfo->cu_mask.ptr, minfo->cu_mask.count, se_mask, 0);



	m = get_mqd(mqd);

	m->compute_static_thread_mgmt_se0 = se_mask[0];

drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c

+1 −1
Original line number Diff line number Diff line
@@ -52,7 +52,7 @@ static void update_cu_mask(struct mqd_manager *mm, void *mqd, 
		return;



	mqd_symmetrically_map_cu_mask(mm,

		minfo->cu_mask.ptr, minfo->cu_mask.count, se_mask);

		minfo->cu_mask.ptr, minfo->cu_mask.count, se_mask, 0);



	m = get_mqd(mqd);

	m->compute_static_thread_mgmt_se0 = se_mask[0];

drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c

+1 −1
Original line number Diff line number Diff line
@@ -71,7 +71,7 @@ static void update_cu_mask(struct mqd_manager *mm, void *mqd, 
	}



	mqd_symmetrically_map_cu_mask(mm,

		minfo->cu_mask.ptr, minfo->cu_mask.count, se_mask);

		minfo->cu_mask.ptr, minfo->cu_mask.count, se_mask, 0);



	m->compute_static_thread_mgmt_se0 = se_mask[0];

	m->compute_static_thread_mgmt_se1 = se_mask[1];