Commit fcfc6cee authored by Yihan Zhu's avatar Yihan Zhu Committed by Alex Deucher
Browse files

drm/amd/display: Enable CM low mem power optimization 



[WHY & HOW]
MPC MCM low mem power optimization still causes color distortion on
first SCE enablement, only forces light sleep for it.

DPP low memory power optimization still needs this bit to save power.

Reviewed-by: default avatarNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: default avatarAlex Hung <alex.hung@amd.com>
Signed-off-by: default avatarYihan Zhu <yihan.zhu@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent ef71bb41

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c

+8 −5
Original line number Diff line number Diff line
@@ -71,21 +71,24 @@ void mpc32_power_on_blnd_lut( 
{

	struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc);



/*

	if (mpc->ctx->dc->debug.enable_mem_low_power.bits.cm) {

		if (power_on) {

			REG_UPDATE(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_1DLUT_MEM_PWR_FORCE, 0);

			REG_WAIT(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_1DLUT_MEM_PWR_STATE, 0, 1, 5);

		} else if (!mpc->ctx->dc->debug.disable_mem_low_power) {

			ASSERT(false);

			/* TODO: change to mpc

			 *  dpp_base->ctx->dc->optimized_required = true;

			 *  dpp_base->deferred_reg_writes.bits.disable_blnd_lut = true;

			 */

			//TODO: change to mpc

			dpp_base->ctx->dc->optimized_required = true;

			dpp_base->deferred_reg_writes.bits.disable_blnd_lut = true;

		}

	} else {

		REG_SET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], 0,

				MPCC_MCM_1DLUT_MEM_PWR_FORCE, power_on == true ? 0 : 1);

	}

*/



	REG_SET(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], 0,

			MPCC_MCM_1DLUT_MEM_PWR_FORCE, power_on == true ? 0 : 1);

}



static enum dc_lut_mode mpc32_get_post1dlut_current(struct mpc *mpc, uint32_t mpcc_id)

drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c

+1 −1
Original line number Diff line number Diff line
@@ -724,7 +724,7 @@ static const struct dc_debug_options debug_defaults_drv = { 
			.i2c = true,

			.dmcu = false, // This is previously known to cause hang on S3 cycles if enabled

			.dscl = true,

			.cm = false,

			.cm = true,

			.mpc = true,

			.optc = true,

			.vpg = true,