Commit fd3ecda3 authored by Niravkumar L Rabara's avatar Niravkumar L Rabara Committed by Borislav Petkov (AMD)
Browse files

EDAC/altera: Handle OCRAM ECC enable after warm reset 



The OCRAM ECC is always enabled either by the BootROM or by the Secure Device
Manager (SDM) during a power-on reset on SoCFPGA.

However, during a warm reset, the OCRAM content is retained to preserve data,
while the control and status registers are reset to their default values. As
a result, ECC must be explicitly re-enabled after a warm reset.

Fixes: 17e47dc6 ("EDAC/altera: Add Stratix10 OCRAM ECC support")
Signed-off-by: default avatarNiravkumar L Rabara <niravkumarlaxmidas.rabara@altera.com>
Signed-off-by: default avatarBorislav Petkov (AMD) <bp@alien8.de>
Acked-by: default avatarDinh Nguyen <dinguyen@kernel.org>
Cc: stable@vger.kernel.org
Link: https://patch.msgid.link/20251111080801.1279401-1-niravkumarlaxmidas.rabara@altera.com
parent 2cf95b9b

drivers/edac/altera_edac.c

+15 −3
Original line number Diff line number Diff line
@@ -1184,10 +1184,22 @@ altr_check_ocram_deps_init(struct altr_edac_device_dev *device) 
	if (ret)

		return ret;



	/* Verify OCRAM has been initialized */

	/*

	 * Verify that OCRAM has been initialized.

	 * During a warm reset, OCRAM contents are retained, but the control

	 * and status registers are reset to their default values. Therefore,

	 * ECC must be explicitly re-enabled in the control register.

	 * Error condition: if INITCOMPLETEA is clear and ECC_EN is already set.

	 */

	if (!ecc_test_bits(ALTR_A10_ECC_INITCOMPLETEA,

			   (base + ALTR_A10_ECC_INITSTAT_OFST)))

			   (base + ALTR_A10_ECC_INITSTAT_OFST))) {

		if (!ecc_test_bits(ALTR_A10_ECC_EN,

				   (base + ALTR_A10_ECC_CTRL_OFST)))

			ecc_set_bits(ALTR_A10_ECC_EN,

				     (base + ALTR_A10_ECC_CTRL_OFST));

		else

			return -ENODEV;

	}



	/* Enable IRQ on Single Bit Error */

	writel(ALTR_A10_ECC_SERRINTEN, (base + ALTR_A10_ECC_ERRINTENS_OFST));