Commit feab6a13 authored by Biju Das's avatar Biju Das Committed by Geert Uytterhoeven
Browse files

arm64: dts: renesas: rz-smarc: Use versa3 clk for audio mclk 



Currently audio mclk uses a fixed clk of 11.2896MHz (multiple of 44.1kHz).
Replace this fixed clk with the programmable versa3 clk that can provide
the clocking to support both 44.1kHz (with a clock of 11.2896MHz) and
48kHz (with a clock of 12.2880MHz), based on audio sampling rate for
playback and record.

Signed-off-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230825090518.87394-1-biju.das.jz@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 75b696a4

arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi

+7 −7
Original line number Diff line number Diff line
@@ -32,12 +32,6 @@ chosen { 
		stdout-path = "serial0:115200n8";

	};



	audio_mclock: audio_mclock {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <11289600>;

	};



	snd_rzg2l: sound {

		compatible = "simple-audio-card";

		simple-audio-card,format = "i2s";
@@ -55,7 +49,7 @@ cpu_dai: simple-audio-card,cpu { 
		};



		codec_dai: simple-audio-card,codec {

			clocks = <&audio_mclock>;

			clocks = <&versa3 2>;

			sound-dai = <&wm8978>;

		};

	};
@@ -76,6 +70,12 @@ vccq_sdhi1: regulator-vccq-sdhi1 { 
		gpios-states = <1>;

		states = <3300000 1>, <1800000 0>;

	};



	x1: x1-clock {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <24000000>;

	};

};



&audio_clk1 {

arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi

+20 −0
Original line number Diff line number Diff line
@@ -110,6 +110,26 @@ wm8978: codec@1a { 
		#sound-dai-cells = <0>;

		reg = <0x1a>;

	};



	versa3: clock-generator@68 {

		compatible = "renesas,5p35023";

		reg = <0x68>;

		#clock-cells = <1>;

		clocks = <&x1>;



		renesas,settings = [

			80 00 11 19 4c 02 23 7f 83 19 08 a9 5f 25 24 bf

			00 14 7a e1 00 00 00 00 01 55 59 bb 3f 30 90 b6

			80 b0 45 c4 95

		];



		assigned-clocks = <&versa3 0>, <&versa3 1>,

				  <&versa3 2>, <&versa3 3>,

				  <&versa3 4>, <&versa3 5>;

		assigned-clock-rates = <24000000>, <11289600>,

				       <11289600>, <12000000>,

				       <25000000>, <12288000>;

	};

};



#if PMOD_MTU3

arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi

+20 −0
Original line number Diff line number Diff line
@@ -126,6 +126,26 @@ wm8978: codec@1a { 
		#sound-dai-cells = <0>;

		reg = <0x1a>;

	};



	versa3: clock-generator@68 {

		compatible = "renesas,5p35023";

		reg = <0x68>;

		#clock-cells = <1>;

		clocks = <&x1>;



		renesas,settings = [

			80 00 11 19 4c 02 23 7f 83 19 08 a9 5f 25 24 bf

			00 14 7a e1 00 00 00 00 01 55 59 bb 3f 30 90 b6

			80 b0 45 c4 95

		];



		assigned-clocks = <&versa3 0>, <&versa3 1>,

				  <&versa3 2>, <&versa3 3>,

				  <&versa3 4>, <&versa3 5>;

		assigned-clock-rates = <24000000>, <11289600>,

				       <11289600>, <12000000>,

				       <25000000>, <12288000>;

	};

};



#if PMOD_MTU3

arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi

+24 −0
Original line number Diff line number Diff line
@@ -20,6 +20,30 @@ &cpu_dai { 
	sound-dai = <&ssi1>;

};



&i2c0 {

	clock-frequency = <400000>;



	versa3: clock-generator@68 {

		compatible = "renesas,5p35023";

		reg = <0x68>;

		#clock-cells = <1>;

		clocks = <&x1>;



		renesas,settings = [

			80 00 11 19 4c 02 23 7f 83 19 08 a9 5f 25 24 bf

			00 14 7a e1 00 00 00 00 01 55 59 bb 3f 30 90 b6

			80 b0 45 c4 95

		];



		assigned-clocks = <&versa3 0>, <&versa3 1>,

				  <&versa3 2>, <&versa3 3>,

				  <&versa3 4>, <&versa3 5>;

		assigned-clock-rates = <24000000>, <11289600>,

				       <11289600>, <12000000>,

				       <25000000>, <12288000>;

	};

};



&i2c1 {

	wm8978: codec@1a {

		compatible = "wlf,wm8978";