Commit fee29f00 authored by Marc Zyngier's avatar Marc Zyngier Committed by Will Deacon
Browse files

arm64: Add HWCAP for self-synchronising virtual counter 



Since userspace can make use of the CNTVSS_EL0 instruction, expose
it via a HWCAP.

Suggested-by: default avatarWill Deacon <will@kernel.org>
Acked-by: default avatarWill Deacon <will@kernel.org>
Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20211017124225.3018098-18-maz@kernel.org


Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent ae976f06

Documentation/arm64/cpu-feature-registers.rst

+10 −2
Original line number Diff line number Diff line
@@ -235,7 +235,15 @@ infrastructure: 
     | DPB                          | [3-0]   |    y    |

     +------------------------------+---------+---------+



  6) ID_AA64MMFR2_EL1 - Memory model feature register 2

  6) ID_AA64MMFR0_EL1 - Memory model feature register 0



     +------------------------------+---------+---------+

     | Name                         |  bits   | visible |

     +------------------------------+---------+---------+

     | ECV                          | [63-60] |    y    |

     +------------------------------+---------+---------+



  7) ID_AA64MMFR2_EL1 - Memory model feature register 2



     +------------------------------+---------+---------+

     | Name                         |  bits   | visible |
@@ -243,7 +251,7 @@ infrastructure: 
     | AT                           | [35-32] |    y    |

     +------------------------------+---------+---------+



  7) ID_AA64ZFR0_EL1 - SVE feature ID register 0

  8) ID_AA64ZFR0_EL1 - SVE feature ID register 0



     +------------------------------+---------+---------+

     | Name                         |  bits   | visible |

Documentation/arm64/elf_hwcaps.rst

+4 −0
Original line number Diff line number Diff line
@@ -247,6 +247,10 @@ HWCAP2_MTE 
    Functionality implied by ID_AA64PFR1_EL1.MTE == 0b0010, as described

    by Documentation/arm64/memory-tagging-extension.rst.



HWCAP2_ECV



    Functionality implied by ID_AA64MMFR0_EL1.ECV == 0b0001.



4. Unused AT_HWCAP bits

-----------------------

arch/arm64/include/asm/hwcap.h

+1 −0
Original line number Diff line number Diff line
@@ -105,6 +105,7 @@ 
#define KERNEL_HWCAP_RNG		__khwcap2_feature(RNG)

#define KERNEL_HWCAP_BTI		__khwcap2_feature(BTI)

#define KERNEL_HWCAP_MTE		__khwcap2_feature(MTE)

#define KERNEL_HWCAP_ECV		__khwcap2_feature(ECV)



/*

 * This yields a mask that user programs can use to figure out what

arch/arm64/include/uapi/asm/hwcap.h

+1 −0
Original line number Diff line number Diff line
@@ -75,5 +75,6 @@ 
#define HWCAP2_RNG		(1 << 16)

#define HWCAP2_BTI		(1 << 17)

#define HWCAP2_MTE		(1 << 18)

#define HWCAP2_ECV		(1 << 19)



#endif /* _UAPI__ASM_HWCAP_H */

arch/arm64/kernel/cpufeature.c

+2 −1
Original line number Diff line number Diff line
@@ -279,7 +279,7 @@ static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = { 
};



static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ECV_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ECV_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_FGT_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EXS_SHIFT, 4, 0),

	/*
@@ -2461,6 +2461,7 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { 
#ifdef CONFIG_ARM64_MTE

	HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_MTE_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_MTE, CAP_HWCAP, KERNEL_HWCAP_MTE),

#endif /* CONFIG_ARM64_MTE */

	HWCAP_CAP(SYS_ID_AA64MMFR0_EL1, ID_AA64MMFR0_ECV_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ECV),

	{},

};