Commit ff2aa649 authored by Sascha Bischoff's avatar Sascha Bischoff Committed by Oliver Upton
Browse files

KVM: arm64: gic-v5: Probe for GICv5 



Add in a probe function for GICv5 which enables support for GICv3
guests on a GICv5 host, if FEAT_GCIE_LEGACY is supported by the
hardware.

Co-authored-by: default avatarTimothy Hayes <timothy.hayes@arm.com>
Signed-off-by: default avatarTimothy Hayes <timothy.hayes@arm.com>
Signed-off-by: default avatarSascha Bischoff <sascha.bischoff@arm.com>
Link: https://lore.kernel.org/r/20250627100847.1022515-6-sascha.bischoff@arm.com


Signed-off-by: default avatarOliver Upton <oliver.upton@linux.dev>
parent c017e49e

arch/arm64/kvm/Makefile

+2 −1
Original line number Diff line number Diff line
@@ -23,7 +23,8 @@ kvm-y += arm.o mmu.o mmio.o psci.o hypercalls.o pvtime.o \ 
	 vgic/vgic-v3.o vgic/vgic-v4.o \

	 vgic/vgic-mmio.o vgic/vgic-mmio-v2.o \

	 vgic/vgic-mmio-v3.o vgic/vgic-kvm-device.o \

	 vgic/vgic-its.o vgic/vgic-debug.o vgic/vgic-v3-nested.o

	 vgic/vgic-its.o vgic/vgic-debug.o vgic/vgic-v3-nested.o \

	 vgic/vgic-v5.o



kvm-$(CONFIG_HW_PERF_EVENTS)  += pmu-emul.o pmu.o

kvm-$(CONFIG_ARM64_PTR_AUTH)  += pauth.o

arch/arm64/kvm/vgic/vgic-init.c

+3 −0
Original line number Diff line number Diff line
@@ -724,6 +724,9 @@ int kvm_vgic_hyp_init(void) 
			kvm_info("GIC system register CPU interface enabled\n");

		}

		break;

	case GIC_V5:

		ret = vgic_v5_probe(gic_kvm_info);

		break;

	default:

		ret = -ENODEV;

	}

arch/arm64/kvm/vgic/vgic-v5.c

0 → 100644
+52 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only



#include <kvm/arm_vgic.h>

#include <linux/irqchip/arm-vgic-info.h>



#include "vgic.h"



/*

 * Probe for a vGICv5 compatible interrupt controller, returning 0 on success.

 * Currently only supports GICv3-based VMs on a GICv5 host, and hence only

 * registers a VGIC_V3 device.

 */

int vgic_v5_probe(const struct gic_kvm_info *info)

{

	u64 ich_vtr_el2;

	int ret;



	if (!info->has_gcie_v3_compat)

		return -ENODEV;



	kvm_vgic_global_state.type = VGIC_V5;

	kvm_vgic_global_state.has_gcie_v3_compat = true;



	/* We only support v3 compat mode - use vGICv3 limits */

	kvm_vgic_global_state.max_gic_vcpus = VGIC_V3_MAX_CPUS;



	kvm_vgic_global_state.vcpu_base = 0;

	kvm_vgic_global_state.vctrl_base = NULL;

	kvm_vgic_global_state.can_emulate_gicv2 = false;

	kvm_vgic_global_state.has_gicv4 = false;

	kvm_vgic_global_state.has_gicv4_1 = false;



	ich_vtr_el2 =  kvm_call_hyp_ret(__vgic_v3_get_gic_config);

	kvm_vgic_global_state.ich_vtr_el2 = (u32)ich_vtr_el2;



	/*

	 * The ListRegs field is 5 bits, but there is an architectural

	 * maximum of 16 list registers. Just ignore bit 4...

	 */

	kvm_vgic_global_state.nr_lr = (ich_vtr_el2 & 0xf) + 1;



	ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V3);

	if (ret) {

		kvm_err("Cannot register GICv3-legacy KVM device.\n");

		return ret;

	}



	static_branch_enable(&kvm_vgic_global_state.gicv3_cpuif);

	kvm_info("GCIE legacy system register CPU interface\n");



	return 0;

}

arch/arm64/kvm/vgic/vgic.h

+2 −0
Original line number Diff line number Diff line
@@ -308,6 +308,8 @@ int vgic_init(struct kvm *kvm); 
void vgic_debug_init(struct kvm *kvm);

void vgic_debug_destroy(struct kvm *kvm);



int vgic_v5_probe(const struct gic_kvm_info *info);



static inline int vgic_v3_max_apr_idx(struct kvm_vcpu *vcpu)

{

	struct vgic_cpu *cpu_if = &vcpu->arch.vgic_cpu;