Commit ff97bc38 authored by Carolina Jubran's avatar Carolina Jubran Committed by Leon Romanovsky
Browse files

net/mlx5: Add RS FEC histogram infrastructure 



Define the Ports Phy Histogram Configuration Register (PPHCR) to expose
RS-FEC histogram bin ranges, and expose a new counter group in the Ports
Performance Counters Register (PPCNT) to report the corresponding
histogram values.

Co-developed-by: default avatarYael Chemla <ychemla@nvidia.com>
Signed-off-by: default avatarYael Chemla <ychemla@nvidia.com>
Signed-off-by: default avatarCarolina Jubran <cjubran@nvidia.com>
Reviewed-by: default avatarDragos Tatulea <dtatulea@nvidia.com>
Signed-off-by: default avatarTariq Toukan <tariqt@nvidia.com>
Link: https://patch.msgid.link/1756884600-520195-1-git-send-email-tariqt@nvidia.com


Signed-off-by: default avatarLeon Romanovsky <leon@kernel.org>
parent 04a3134f

include/linux/mlx5/device.h

+1 −0
Original line number Diff line number Diff line
@@ -1525,6 +1525,7 @@ enum { 
	MLX5_PHYSICAL_LAYER_RECOVERY_GROUP    = 0x1a,

	MLX5_INFINIBAND_PORT_COUNTERS_GROUP   = 0x20,

	MLX5_INFINIBAND_EXTENDED_PORT_COUNTERS_GROUP = 0x21,

	MLX5_RS_FEC_HISTOGRAM_GROUP = 0x23,

};



enum {

include/linux/mlx5/driver.h

+1 −0
Original line number Diff line number Diff line
@@ -130,6 +130,7 @@ enum { 
	MLX5_REG_PDDR		 = 0x5031,

	MLX5_REG_PMLP		 = 0x5002,

	MLX5_REG_PPLM		 = 0x5023,

	MLX5_REG_PPHCR		 = 0x503E,

	MLX5_REG_PCAM		 = 0x507f,

	MLX5_REG_NODE_DESC	 = 0x6001,

	MLX5_REG_HOST_ENDIANNESS = 0x7004,

include/linux/mlx5/mlx5_ifc.h

+29 −0
Original line number Diff line number Diff line
@@ -4901,6 +4901,11 @@ union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 
	u8         reserved_at_0[0x20];

};



struct mlx5_ifc_rs_histogram_cntrs_bits {

	u8         hist[16][0x40];

	u8         reserved_at_400[0x2c0];

};



union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {

	struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;

	struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
@@ -4915,6 +4920,7 @@ union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 
	struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;

	struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;

	struct mlx5_ifc_phys_layer_recovery_cntrs_bits phys_layer_recovery_cntrs;

	struct mlx5_ifc_rs_histogram_cntrs_bits rs_histogram_cntrs;

	u8         reserved_at_0[0x7c0];

};
@@ -11738,6 +11744,28 @@ struct mlx5_ifc_mtctr_reg_bits { 
	u8         second_clock_timestamp[0x40];

};



struct mlx5_ifc_bin_range_layout_bits {

	u8         reserved_at_0[0xa];

	u8         high_val[0x6];

	u8         reserved_at_10[0xa];

	u8         low_val[0x6];

};



struct mlx5_ifc_pphcr_reg_bits {

	u8         active_hist_type[0x4];

	u8         reserved_at_4[0x4];

	u8         local_port[0x8];

	u8         reserved_at_10[0x10];



	u8         reserved_at_20[0x8];

	u8         num_of_bins[0x8];

	u8         reserved_at_30[0x10];



	u8         reserved_at_40[0x40];



	struct mlx5_ifc_bin_range_layout_bits bin_range[16];

};



union mlx5_ifc_ports_control_registers_document_bits {

	struct mlx5_ifc_bufferx_reg_bits bufferx_reg;

	struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
@@ -11804,6 +11832,7 @@ union mlx5_ifc_ports_control_registers_document_bits { 
	struct mlx5_ifc_mtmp_reg_bits mtmp_reg;

	struct mlx5_ifc_mtptm_reg_bits mtptm_reg;

	struct mlx5_ifc_mtctr_reg_bits mtctr_reg;

	struct mlx5_ifc_pphcr_reg_bits pphcr_reg;

	u8         reserved_at_0[0x60e0];

};