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drm/amdgpu: Add XCC inst to PASID TLB flushing
Add XCC instance to select the correct KIQ ring when flushing TLBs on a multi-XCC setup. Signed-off-by: Mukul Joshi <mukul.joshi@amd.com> Tested-by: Amber Lin <Amber.Lin@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
committed by
Alex Deucher
parent
e2069a7b08
commit
f87f686482
@@ -2052,6 +2052,7 @@ void kfd_flush_tlb(struct kfd_process_device *pdd, enum TLB_FLUSH_TYPE type)
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struct amdgpu_vm *vm = drm_priv_to_vm(pdd->drm_priv);
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uint64_t tlb_seq = amdgpu_vm_tlb_seq(vm);
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struct kfd_node *dev = pdd->dev;
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int xcc = 0;
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/*
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* It can be that we race and lose here, but that is extremely unlikely
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@@ -2069,8 +2070,10 @@ void kfd_flush_tlb(struct kfd_process_device *pdd, enum TLB_FLUSH_TYPE type)
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amdgpu_amdkfd_flush_gpu_tlb_vmid(dev->adev,
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pdd->qpd.vmid);
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} else {
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amdgpu_amdkfd_flush_gpu_tlb_pasid(dev->adev,
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pdd->process->pasid, type);
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for (xcc = 0; xcc < dev->num_xcc_per_node; xcc++)
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amdgpu_amdkfd_flush_gpu_tlb_pasid(dev->adev,
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pdd->process->pasid, type,
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dev->start_xcc_id + xcc);
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}
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}
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