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https://git.kernel.org/pub/scm/linux/kernel/git/netfilter/nf.git
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3a086236c6
Introduce a new clock PLLA for SpacemiT's K3 SoC which has a different register layout comparing to previous PPL type. And, It is configured by swcr1, swcr3 and swcr2 BIT[15:8]. Link: https://lore.kernel.org/r/20260108-k3-clk-v5-3-42a11b74ad58@gentoo.org Signed-off-by: Yixun Lan <dlan@gentoo.org>
60 lines
1.1 KiB
C
60 lines
1.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2024 SpacemiT Technology Co. Ltd
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* Copyright (c) 2024-2025 Haylen Chu <heylenay@4d2.org>
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*/
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#ifndef _CCU_COMMON_H_
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#define _CCU_COMMON_H_
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#include <linux/clk-provider.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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struct ccu_common {
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struct regmap *regmap;
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struct regmap *lock_regmap;
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union {
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/* For DDN and MIX */
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struct {
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u32 reg_ctrl;
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u32 reg_fc;
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u32 mask_fc;
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};
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/* For PLL */
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struct {
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u32 reg_swcr1;
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u32 reg_swcr2;
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u32 reg_swcr3;
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};
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};
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struct clk_hw hw;
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};
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static inline struct ccu_common *hw_to_ccu_common(struct clk_hw *hw)
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{
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return container_of(hw, struct ccu_common, hw);
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}
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struct spacemit_ccu_data {
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const char *reset_name;
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struct clk_hw **hws;
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size_t num;
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};
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#define ccu_read(c, reg) \
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({ \
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u32 tmp; \
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regmap_read((c)->regmap, (c)->reg_##reg, &tmp); \
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tmp; \
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})
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#define ccu_update(c, reg, mask, val) \
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regmap_update_bits((c)->regmap, (c)->reg_##reg, mask, val)
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int spacemit_ccu_probe(struct platform_device *pdev, const char *compat);
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#endif /* _CCU_COMMON_H_ */
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