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221cadb9c6
Based on research and ideas by Alexandre and Christian. VCE1 actually executes its code from the VCPU BO. Due to various hardware limitations, the VCE1 requires the VCPU BO to be in the low 32 bit address range. However, VRAM is typically mapped at the high address range, which means the VCPU can't access VRAM through the FB aperture. To solve this, we write a few page table entries to map the VCPU BO in the GART address range. And we make sure that the GART is located at the low address range. That way the VCE1 can access the VCPU BO. v2: - Adjust to v2 of the GART helper commit. - Add empty line to multi-line comment. v3: - Instead of relying on gmc_v6 to set the GART space before GTT, add a new function amdgpu_vce_required_gart_pages() which is called from amdgpu_gtt_mgr_init() directly. Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Co-developed-by: Alexandre Demers <alexandre.f.demers@gmail.com> Signed-off-by: Alexandre Demers <alexandre.f.demers@gmail.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
83 lines
3.4 KiB
C
83 lines
3.4 KiB
C
/*
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* Copyright 2014 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __AMDGPU_VCE_H__
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#define __AMDGPU_VCE_H__
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#define AMDGPU_MAX_VCE_HANDLES 16
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#define AMDGPU_VCE_FIRMWARE_OFFSET 256
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#define AMDGPU_VCE_HARVEST_VCE0 (1 << 0)
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#define AMDGPU_VCE_HARVEST_VCE1 (1 << 1)
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#define AMDGPU_VCE_FW_53_45 ((53 << 24) | (45 << 16))
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struct amdgpu_vce {
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struct amdgpu_bo *vcpu_bo;
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uint64_t gpu_addr;
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void *cpu_addr;
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void *saved_bo;
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unsigned fw_version;
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unsigned fb_version;
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atomic_t handles[AMDGPU_MAX_VCE_HANDLES];
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struct drm_file *filp[AMDGPU_MAX_VCE_HANDLES];
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uint32_t img_size[AMDGPU_MAX_VCE_HANDLES];
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struct delayed_work idle_work;
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struct mutex idle_mutex;
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const struct firmware *fw; /* VCE firmware */
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struct amdgpu_ring ring[AMDGPU_MAX_VCE_RINGS];
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struct amdgpu_irq_src irq;
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unsigned harvest_config;
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struct drm_sched_entity entity;
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uint32_t srbm_soft_reset;
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unsigned num_rings;
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uint32_t keyselect;
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};
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int amdgpu_vce_early_init(struct amdgpu_device *adev);
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int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size);
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int amdgpu_vce_sw_fini(struct amdgpu_device *adev);
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int amdgpu_vce_entity_init(struct amdgpu_device *adev, struct amdgpu_ring *ring);
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int amdgpu_vce_suspend(struct amdgpu_device *adev);
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int amdgpu_vce_resume(struct amdgpu_device *adev);
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void amdgpu_vce_free_handles(struct amdgpu_device *adev, struct drm_file *filp);
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u32 amdgpu_vce_required_gart_pages(struct amdgpu_device *adev);
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int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, struct amdgpu_job *job,
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struct amdgpu_ib *ib);
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int amdgpu_vce_ring_parse_cs_vm(struct amdgpu_cs_parser *p,
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struct amdgpu_job *job,
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struct amdgpu_ib *ib);
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void amdgpu_vce_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_job *job,
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struct amdgpu_ib *ib, uint32_t flags);
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void amdgpu_vce_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
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unsigned flags);
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int amdgpu_vce_ring_test_ring(struct amdgpu_ring *ring);
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int amdgpu_vce_ring_test_ib(struct amdgpu_ring *ring, long timeout);
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void amdgpu_vce_ring_begin_use(struct amdgpu_ring *ring);
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void amdgpu_vce_ring_end_use(struct amdgpu_ring *ring);
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unsigned amdgpu_vce_ring_get_emit_ib_size(struct amdgpu_ring *ring);
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unsigned amdgpu_vce_ring_get_dma_frame_size(struct amdgpu_ring *ring);
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enum amdgpu_ring_priority_level amdgpu_vce_get_ring_prio(int ring);
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#endif
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