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d9649a7e4d
Add device tree bindings for TI's TUSB73x0 PCIe-to-USB 3.0 xHCI host controller. The controller supports software configuration through PCIe registers, such as controlling the PWRONx polarity via the USB control register (E0h). Datasheet: https://www.ti.com/lit/ds/symlink/tusb7320.pdf Signed-off-by: Parth Pancholi <parth.pancholi@toradex.com> Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20241029072444.8827-2-francesco@dolcini.it Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
56 lines
1.4 KiB
YAML
56 lines
1.4 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/usb/ti,tusb73x0-pci.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: TUSB73x0 USB 3.0 xHCI Host Controller (PCIe)
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maintainers:
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- Francesco Dolcini <francesco.dolcini@toradex.com>
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description:
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TUSB73x0 USB 3.0 xHCI Host Controller via PCIe x1 Gen2 interface.
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The TUSB7320 supports up to two downstream ports, the TUSB7340 supports up
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to four downstream ports, both variants share the same PCI device ID.
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properties:
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compatible:
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const: pci104c,8241
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reg:
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maxItems: 1
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ti,pwron-active-high:
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$ref: /schemas/types.yaml#/definitions/flag
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description:
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Configure the polarity of the PWRONx# signals. When this is present, the
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PWRONx# pins are active high and their internal pull-down resistors are
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disabled. When this is absent, the PWRONx# pins are active low (default)
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and their internal pull-down resistors are enabled.
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required:
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- compatible
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- reg
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allOf:
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- $ref: usb-xhci.yaml
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additionalProperties: false
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examples:
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- |
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pcie@0 {
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reg = <0x0 0x1000>;
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ranges = <0x02000000 0x0 0x100000 0x10000000 0x0 0x0>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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usb@0 {
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compatible = "pci104c,8241";
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reg = <0x0 0x0 0x0 0x0 0x0>;
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ti,pwron-active-high;
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};
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};
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