Networking changes for 6.18.

Core & protocols
 ----------------
 
  - Improve drop account scalability on NUMA hosts for RAW and UDP sockets
    and the backlog, almost doubling the Pps capacity under DoS.
 
  - Optimize the UDP RX performance under stress, reducing contention,
    revisiting the binary layout of the involved data structs and
    implementing NUMA-aware locking. This improves UDP RX performance by
    an additional 50%, even more under extreme conditions.
 
  - Add support for PSP encryption of TCP connections; this mechanism has
    some similarities with IPsec and TLS, but offers superior HW offloads
    capabilities.
 
  - Ongoing work to support Accurate ECN for TCP. AccECN allows more than
    one congestion notification signal per RTT and is a building block for
    Low Latency, Low Loss, and Scalable Throughput (L4S).
 
  - Reorganize the TCP socket binary layout for data locality, reducing
    the number of touched cachelines in the fastpath.
 
  - Refactor skb deferral free to better scale on large multi-NUMA hosts,
    this improves TCP and UDP RX performances significantly on such HW.
 
  - Increase the default socket memory buffer limits from 256K to 4M to
    better fit modern link speeds.
 
  - Improve handling of setups with a large number of nexthop, making dump
    operating scaling linearly and avoiding unneeded synchronize_rcu() on
    delete.
 
  - Improve bridge handling of VLAN FDB, storing a single entry per bridge
    instead of one entry per port; this makes the dump order of magnitude
    faster on large switches.
 
  - Restore IP ID correctly for encapsulated packets at GSO segmentation
    time, allowing GRO to merge packets in more scenarios.
 
  - Improve netfilter matching performance on large sets.
 
  - Improve MPTCP receive path performance by leveraging recently
    introduced core infrastructure (skb deferral free) and adopting recent
    TCP autotuning changes.
 
  - Allow bridges to redirect to a backup port when the bridge port is
    administratively down.
 
  - Introduce MPTCP 'laminar' endpoint that con be used only once per
    connection and simplify common MPTCP setups.
 
  - Add RCU safety to dst->dev, closing a lot of possible races.
 
  - A significant crypto library API for SCTP, MPTCP and IPv6 SR, reducing
    code duplication.
 
  - Supports pulling data from an skb frag into the linear area of an XDP
    buffer.
 
 Things we sprinkled into general kernel code
 --------------------------------------------
 
  - Generate netlink documentation from YAML using an integrated
    YAML parser.
 
 Driver API
 ----------
 
  - Support using IPv6 Flow Label in Rx hash computation and RSS queue
    selection.
 
  - Introduce API for fetching the DMA device for a given queue, allowing
    TCP zerocopy RX on more H/W setups.
 
  - Make XDP helpers compatible with unreadable memory, allowing more
    easily building DevMem-enabled drivers with a unified XDP/skbs
    datapath.
 
  - Add a new dedicated ethtool callback enabling drivers to provide the
    number of RX rings directly, improving efficiency and clarity in RX
    ring queries and RSS configuration.
 
  - Introduce a burst period for the health reporter, allowing better
    handling of multiple errors due to the same root cause.
 
  - Support for DPLL phase offset exponential moving average, controlling
    the average smoothing factor.
 
 Device drivers
 --------------
 
  - Add a new Huawei driver for 3rd gen NIC (hinic3).
 
  - Add a new SpacemiT driver for K1 ethernet MAC.
 
  - Add a generic abstraction for shared memory communication devices
    (dibps)
 
  - Ethernet high-speed NICs:
    - nVidia/Mellanox:
      - Use multiple per-queue doorbell, to avoid MMIO contention issues
      - support adjacent functions, allowing them to delegate their
        SR-IOV VFs to sibling PFs
      - support RSS for IPSec offload
      - support exposing raw cycle counters in PTP and mlx5
      - support for disabling host PFs.
    - Intel (100G, ice, idpf):
      - ice: support for SRIOV VFs over an Active-Active link aggregate
      - ice: support for firmware logging via debugfs
      - ice: support for Earliest TxTime First (ETF) hardware offload
      - idpf: support basic XDP functionalities and XSk
    - Broadcom (bnxt):
      - support Hyper-V VF ID
      - dynamic SRIOV resource allocations for RoCE
    - Meta (fbnic):
      - support queue API, zero-copy Rx and Tx
      - support basic XDP functionalities
      - devlink health support for FW crashes and OTP mem corruptions
      - expand hardware stats coverage to FEC, PHY, and Pause
    - Wangxun:
      - support ethtool coalesce options
      - support for multiple RSS contexts
 
  - Ethernet virtual:
    - Macsec:
      - replace custom netlink attribute checks with policy-level checks
    - Bonding:
      - support aggregator selection based on port priority
    - Microsoft vNIC:
      - use page pool fragments for RX buffers instead of full pages to
        improve memory efficiency
 
  - Ethernet NICs consumer, and embedded:
    - Qualcomm: support Ethernet function for IPQ9574 SoC
    - Airoha: implement wlan offloading via NPU
    - Freescale
      - enetc: add NETC timer PTP driver and add PTP support
      - fec: enable the Jumbo frame support for i.MX8QM
    - Renesas (R-Car S4): support HW offloading for layer 2 switching
      - support for RZ/{T2H, N2H} SoCs
    - Cadence (macb): support TAPRIO traffic scheduling
    - TI:
      - support for Gigabit ICSS ethernet SoC (icssm-prueth)
    - Synopsys (stmmac): a lot of cleanups
 
  - Ethernet PHYs:
    - Support 10g-qxgmi phy-mode for AQR412C, Felix DSA and Lynx PCS
      driver
    - Support bcm63268 GPHY power control
    - Support for Micrel lan8842 PHY and PTP
    - Support for Aquantia AQR412 and AQR115
 
  - CAN:
    - a large CAN-XL preparation work
    - reorganize raw_sock and uniqframe struct to minimize memory usage
    - rcar_canfd: update the CAN-FD handling
 
  - WiFi:
    - extended Neighbor Awareness Networking (NAN) support
    - S1G channel representation cleanup
    - improve S1G support
 
  - WiFi drivers:
    - Intel (iwlwifi):
      - major refactor and cleanup
    - Broadcom (brcm80211):
      - support for AP isolation
    - RealTek (rtw88/89) rtw88/89:
      - preparation work for RTL8922DE support
    - MediaTek (mt76):
      - HW restart improvements
      - MLO support
    - Qualcomm/Atheros (ath10k_
      - GTK rekey fixes
 
  - Bluetooth drivers:
    - btusb: support for several new IDs for MT7925
    - btintel: support for BlazarIW core
    - btintel_pcie: support for _suspend() / _resume()
    - btintel_pcie: support for Scorpious, Panther Lake-H484 IDs
 
 Signed-off-by: Paolo Abeni <pabeni@redhat.com>
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Merge tag 'net-next-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next

Pull networking updates from Paolo Abeni:
 "Core & protocols:

   - Improve drop account scalability on NUMA hosts for RAW and UDP
     sockets and the backlog, almost doubling the Pps capacity under DoS

   - Optimize the UDP RX performance under stress, reducing contention,
     revisiting the binary layout of the involved data structs and
     implementing NUMA-aware locking. This improves UDP RX performance
     by an additional 50%, even more under extreme conditions

   - Add support for PSP encryption of TCP connections; this mechanism
     has some similarities with IPsec and TLS, but offers superior HW
     offloads capabilities

   - Ongoing work to support Accurate ECN for TCP. AccECN allows more
     than one congestion notification signal per RTT and is a building
     block for Low Latency, Low Loss, and Scalable Throughput (L4S)

   - Reorganize the TCP socket binary layout for data locality, reducing
     the number of touched cachelines in the fastpath

   - Refactor skb deferral free to better scale on large multi-NUMA
     hosts, this improves TCP and UDP RX performances significantly on
     such HW

   - Increase the default socket memory buffer limits from 256K to 4M to
     better fit modern link speeds

   - Improve handling of setups with a large number of nexthop, making
     dump operating scaling linearly and avoiding unneeded
     synchronize_rcu() on delete

   - Improve bridge handling of VLAN FDB, storing a single entry per
     bridge instead of one entry per port; this makes the dump order of
     magnitude faster on large switches

   - Restore IP ID correctly for encapsulated packets at GSO
     segmentation time, allowing GRO to merge packets in more scenarios

   - Improve netfilter matching performance on large sets

   - Improve MPTCP receive path performance by leveraging recently
     introduced core infrastructure (skb deferral free) and adopting
     recent TCP autotuning changes

   - Allow bridges to redirect to a backup port when the bridge port is
     administratively down

   - Introduce MPTCP 'laminar' endpoint that con be used only once per
     connection and simplify common MPTCP setups

   - Add RCU safety to dst->dev, closing a lot of possible races

   - A significant crypto library API for SCTP, MPTCP and IPv6 SR,
     reducing code duplication

   - Supports pulling data from an skb frag into the linear area of an
     XDP buffer

  Things we sprinkled into general kernel code:

   - Generate netlink documentation from YAML using an integrated YAML
     parser

  Driver API:

   - Support using IPv6 Flow Label in Rx hash computation and RSS queue
     selection

   - Introduce API for fetching the DMA device for a given queue,
     allowing TCP zerocopy RX on more H/W setups

   - Make XDP helpers compatible with unreadable memory, allowing more
     easily building DevMem-enabled drivers with a unified XDP/skbs
     datapath

   - Add a new dedicated ethtool callback enabling drivers to provide
     the number of RX rings directly, improving efficiency and clarity
     in RX ring queries and RSS configuration

   - Introduce a burst period for the health reporter, allowing better
     handling of multiple errors due to the same root cause

   - Support for DPLL phase offset exponential moving average,
     controlling the average smoothing factor

  Device drivers:

   - Add a new Huawei driver for 3rd gen NIC (hinic3)

   - Add a new SpacemiT driver for K1 ethernet MAC

   - Add a generic abstraction for shared memory communication
     devices (dibps)

   - Ethernet high-speed NICs:
      - nVidia/Mellanox:
         - Use multiple per-queue doorbell, to avoid MMIO contention
           issues
         - support adjacent functions, allowing them to delegate their
           SR-IOV VFs to sibling PFs
         - support RSS for IPSec offload
         - support exposing raw cycle counters in PTP and mlx5
         - support for disabling host PFs.
      - Intel (100G, ice, idpf):
         - ice: support for SRIOV VFs over an Active-Active link
           aggregate
         - ice: support for firmware logging via debugfs
         - ice: support for Earliest TxTime First (ETF) hardware offload
         - idpf: support basic XDP functionalities and XSk
      - Broadcom (bnxt):
         - support Hyper-V VF ID
         - dynamic SRIOV resource allocations for RoCE
      - Meta (fbnic):
         - support queue API, zero-copy Rx and Tx
         - support basic XDP functionalities
         - devlink health support for FW crashes and OTP mem corruptions
         - expand hardware stats coverage to FEC, PHY, and Pause
      - Wangxun:
         - support ethtool coalesce options
         - support for multiple RSS contexts

   - Ethernet virtual:
      - Macsec:
         - replace custom netlink attribute checks with policy-level
           checks
      - Bonding:
         - support aggregator selection based on port priority
      - Microsoft vNIC:
         - use page pool fragments for RX buffers instead of full pages
           to improve memory efficiency

   - Ethernet NICs consumer, and embedded:
      - Qualcomm: support Ethernet function for IPQ9574 SoC
      - Airoha: implement wlan offloading via NPU
      - Freescale
         - enetc: add NETC timer PTP driver and add PTP support
         - fec: enable the Jumbo frame support for i.MX8QM
      - Renesas (R-Car S4):
         - support HW offloading for layer 2 switching
         - support for RZ/{T2H, N2H} SoCs
      - Cadence (macb): support TAPRIO traffic scheduling
      - TI:
         - support for Gigabit ICSS ethernet SoC (icssm-prueth)
      - Synopsys (stmmac): a lot of cleanups

   - Ethernet PHYs:
      - Support 10g-qxgmi phy-mode for AQR412C, Felix DSA and Lynx PCS
        driver
      - Support bcm63268 GPHY power control
      - Support for Micrel lan8842 PHY and PTP
      - Support for Aquantia AQR412 and AQR115

   - CAN:
      - a large CAN-XL preparation work
      - reorganize raw_sock and uniqframe struct to minimize memory
        usage
      - rcar_canfd: update the CAN-FD handling

   - WiFi:
      - extended Neighbor Awareness Networking (NAN) support
      - S1G channel representation cleanup
      - improve S1G support

   - WiFi drivers:
      - Intel (iwlwifi):
         - major refactor and cleanup
      - Broadcom (brcm80211):
         - support for AP isolation
      - RealTek (rtw88/89) rtw88/89:
         - preparation work for RTL8922DE support
      - MediaTek (mt76):
         - HW restart improvements
         - MLO support
      - Qualcomm/Atheros (ath10k):
         - GTK rekey fixes

   - Bluetooth drivers:
      - btusb: support for several new IDs for MT7925
      - btintel: support for BlazarIW core
      - btintel_pcie: support for _suspend() / _resume()
      - btintel_pcie: support for Scorpious, Panther Lake-H484 IDs"

* tag 'net-next-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next: (1536 commits)
  net: stmmac: Add support for Allwinner A523 GMAC200
  dt-bindings: net: sun8i-emac: Add A523 GMAC200 compatible
  Revert "Documentation: net: add flow control guide and document ethtool API"
  octeontx2-pf: fix bitmap leak
  octeontx2-vf: fix bitmap leak
  net/mlx5e: Use extack in set rxfh callback
  net/mlx5e: Introduce mlx5e_rss_params for RSS configuration
  net/mlx5e: Introduce mlx5e_rss_init_params
  net/mlx5e: Remove unused mdev param from RSS indir init
  net/mlx5: Improve QoS error messages with actual depth values
  net/mlx5e: Prevent entering switchdev mode with inconsistent netns
  net/mlx5: HWS, Generalize complex matchers
  net/mlx5: Improve write-combining test reliability for ARM64 Grace CPUs
  selftests/net: add tcp_port_share to .gitignore
  Revert "net/mlx5e: Update and set Xon/Xoff upon MTU set"
  net: add NUMA awareness to skb_attempt_defer_free()
  net: use llist for sd->defer_list
  net: make softnet_data.defer_count an atomic
  selftests: drv-net: psp: add tests for destroying devices
  selftests: drv-net: psp: add test for auto-adjusting TCP MSS
  ...
This commit is contained in:
Linus Torvalds 2025-10-02 15:17:01 -07:00
commit 07fdad3a93
1549 changed files with 79558 additions and 27791 deletions

View File

@ -745,6 +745,8 @@ Sriram Yagnaraman <sriram.yagnaraman@ericsson.com> <sriram.yagnaraman@est.tech>
Stanislav Fomichev <sdf@fomichev.me> <sdf@google.com>
Stanislav Fomichev <sdf@fomichev.me> <stfomichev@gmail.com>
Stefan Wahren <wahrenst@gmx.net> <stefan.wahren@i2se.com>
Stéphane Grosjean <stephane.grosjean@hms-networks.com> <s.grosjean@peak-system.com>
Stéphane Grosjean <stephane.grosjean@hms-networks.com> <stephane.grosjean@free.fr>
Stéphane Witzmann <stephane.witzmann@ubpmes.univ-bpclermont.fr>
Stephen Hemminger <stephen@networkplumber.org> <shemminger@linux-foundation.org>
Stephen Hemminger <stephen@networkplumber.org> <shemminger@osdl.org>
@ -822,6 +824,7 @@ Veerabhadrarao Badiganti <quic_vbadigan@quicinc.com> <vbadigan@codeaurora.org>
Venkateswara Naralasetty <quic_vnaralas@quicinc.com> <vnaralas@codeaurora.org>
Vikash Garodia <vikash.garodia@oss.qualcomm.com> <vgarodia@codeaurora.org>
Vikash Garodia <vikash.garodia@oss.qualcomm.com> <quic_vgarodia@quicinc.com>
Vincent Mailhol <mailhol@kernel.org> <mailhol.vincent@wanadoo.fr>
Vinod Koul <vkoul@kernel.org> <vinod.koul@intel.com>
Vinod Koul <vkoul@kernel.org> <vinod.koul@linux.intel.com>
Vinod Koul <vkoul@kernel.org> <vkoul@infradead.org>

View File

@ -0,0 +1,8 @@
What: /sys/bus/platform/devices/xxx/version
Date: Sep 2025
Contact: netdev@vger.kernel.org
Description: Reports the version of the PEF2256 framer
Access: Read
Valid values: Represented as string

View File

@ -104,22 +104,6 @@ quiet_cmd_sphinx = SPHINX $@ --> file://$(abspath $(BUILDDIR)/$3/$4)
cp $(if $(patsubst /%,,$(DOCS_CSS)),$(abspath $(srctree)/$(DOCS_CSS)),$(DOCS_CSS)) $(BUILDDIR)/$3/_static/; \
fi
YNL_INDEX:=$(srctree)/Documentation/networking/netlink_spec/index.rst
YNL_RST_DIR:=$(srctree)/Documentation/networking/netlink_spec
YNL_YAML_DIR:=$(srctree)/Documentation/netlink/specs
YNL_TOOL:=$(srctree)/tools/net/ynl/pyynl/ynl_gen_rst.py
YNL_RST_FILES_TMP := $(patsubst %.yaml,%.rst,$(wildcard $(YNL_YAML_DIR)/*.yaml))
YNL_RST_FILES := $(patsubst $(YNL_YAML_DIR)%,$(YNL_RST_DIR)%, $(YNL_RST_FILES_TMP))
$(YNL_INDEX): $(YNL_RST_FILES)
$(Q)$(YNL_TOOL) -o $@ -x
$(YNL_RST_DIR)/%.rst: $(YNL_YAML_DIR)/%.yaml $(YNL_TOOL)
$(Q)$(YNL_TOOL) -i $< -o $@
htmldocs texinfodocs latexdocs epubdocs xmldocs: $(YNL_INDEX)
htmldocs:
@$(srctree)/scripts/sphinx-pre-install --version-check
@+$(foreach var,$(SPHINXDIRS),$(call loop_cmd,sphinx,html,$(var),,$(var)))
@ -186,7 +170,6 @@ refcheckdocs:
$(Q)cd $(srctree);scripts/documentation-file-ref-check
cleandocs:
$(Q)rm -f $(YNL_INDEX) $(YNL_RST_FILES)
$(Q)rm -rf $(BUILDDIR)
$(Q)$(MAKE) BUILDDIR=$(abspath $(BUILDDIR)) $(build)=Documentation/userspace-api/media clean

View File

@ -222,6 +222,8 @@ rmem_max
The maximum receive socket buffer size in bytes.
Default: 4194304
rps_default_mask
----------------
@ -247,6 +249,8 @@ wmem_max
The maximum send socket buffer size in bytes.
Default: 4194304
message_burst and message_cost
------------------------------

View File

@ -42,6 +42,15 @@ exclude_patterns = []
dyn_include_patterns = []
dyn_exclude_patterns = ["output"]
# Currently, only netlink/specs has a parser for yaml.
# Prefer using include patterns if available, as it is faster
if has_include_patterns:
dyn_include_patterns.append("netlink/specs/*.yaml")
else:
dyn_exclude_patterns.append("netlink/*.yaml")
dyn_exclude_patterns.append("devicetree/bindings/**.yaml")
dyn_exclude_patterns.append("core-api/kho/bindings/**.yaml")
# Properly handle include/exclude patterns
# ----------------------------------------
@ -102,12 +111,12 @@ extensions = [
"kernel_include",
"kfigure",
"maintainers_include",
"parser_yaml",
"rstFlatTable",
"sphinx.ext.autosectionlabel",
"sphinx.ext.ifconfig",
"translations",
]
# Since Sphinx version 3, the C function parser is more pedantic with regards
# to type checking. Due to that, having macros at c:function cause problems.
# Those needed to be escaped by using c_id_attributes[] array
@ -204,10 +213,11 @@ else:
# Add any paths that contain templates here, relative to this directory.
templates_path = ["sphinx/templates"]
# The suffix(es) of source filenames.
# You can specify multiple suffix as a list of string:
# source_suffix = ['.rst', '.md']
source_suffix = '.rst'
# The suffixes of source filenames that will be automatically parsed
source_suffix = {
".rst": "restructuredtext",
".yaml": "yaml",
}
# The encoding of source files.
# source_encoding = 'utf-8-sig'

View File

@ -41,9 +41,21 @@ properties:
- description: wlan irq line5
memory-region:
maxItems: 1
description:
Memory used to store NPU firmware binary.
oneOf:
- items:
- description: NPU firmware binary region
- items:
- description: NPU firmware binary region
- description: NPU wlan offload RX buffers region
- description: NPU wlan offload TX buffers region
- description: NPU wlan offload TX packet identifiers region
memory-region-names:
items:
- const: firmware
- const: pkt
- const: tx-pkt
- const: tx-bufid
required:
- compatible
@ -79,6 +91,8 @@ examples:
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
memory-region = <&npu_binary>;
memory-region = <&npu_firmware>, <&npu_pkt>, <&npu_txpkt>,
<&npu_txbufid>;
memory-region-names = "firmware", "pkt", "tx-pkt", "tx-bufid";
};
};

View File

@ -33,6 +33,15 @@ properties:
- items:
- description: phandle to SRAM
- description: register value for device
dmas:
items:
- description: RX DMA Channel
- description: TX DMA Channel
dma-names:
items:
- const: rx
- const: tx
required:
- compatible

View File

@ -10,6 +10,21 @@ maintainers:
- Chen-Yu Tsai <wens@csie.org>
- Maxime Ripard <mripard@kernel.org>
# We need a select here so we don't match all nodes with 'snps,dwmac'
select:
properties:
compatible:
contains:
enum:
- allwinner,sun8i-a83t-emac
- allwinner,sun8i-h3-emac
- allwinner,sun8i-r40-gmac
- allwinner,sun8i-v3s-emac
- allwinner,sun50i-a64-emac
- allwinner,sun55i-a523-gmac200
required:
- compatible
properties:
compatible:
oneOf:
@ -26,6 +41,9 @@ properties:
- allwinner,sun50i-h616-emac0
- allwinner,sun55i-a523-gmac0
- const: allwinner,sun50i-a64-emac
- items:
- const: allwinner,sun55i-a523-gmac200
- const: snps,dwmac-4.20a
reg:
maxItems: 1
@ -37,14 +55,21 @@ properties:
const: macirq
clocks:
maxItems: 1
minItems: 1
maxItems: 2
clock-names:
const: stmmaceth
minItems: 1
items:
- const: stmmaceth
- const: mbus
phy-supply:
description: PHY regulator
power-domains:
maxItems: 1
syscon:
$ref: /schemas/types.yaml#/definitions/phandle
description:
@ -191,6 +216,42 @@ allOf:
- mdio-parent-bus
- mdio@1
- if:
properties:
compatible:
contains:
const: allwinner,sun55i-a523-gmac200
then:
properties:
clocks:
minItems: 2
clock-names:
minItems: 2
tx-internal-delay-ps:
default: 0
minimum: 0
maximum: 700
multipleOf: 100
description:
External RGMII PHY TX clock delay chain value in ps.
rx-internal-delay-ps:
default: 0
minimum: 0
maximum: 3100
multipleOf: 100
description:
External RGMII PHY TX clock delay chain value in ps.
required:
- power-domains
else:
properties:
clocks:
maxItems: 1
clock-names:
maxItems: 1
power-domains: false
unevaluatedProperties: false
examples:
@ -323,4 +384,34 @@ examples:
};
};
- |
ethernet@4510000 {
compatible = "allwinner,sun55i-a523-gmac200",
"snps,dwmac-4.20a";
reg = <0x04510000 0x10000>;
clocks = <&ccu 117>, <&ccu 79>;
clock-names = "stmmaceth", "mbus";
resets = <&ccu 43>;
reset-names = "stmmaceth";
interrupts = <0 47 4>;
interrupt-names = "macirq";
pinctrl-names = "default";
pinctrl-0 = <&rgmii1_pins>;
power-domains = <&pck600 4>;
syscon = <&syscon>;
phy-handle = <&ext_rgmii_phy_1>;
phy-mode = "rgmii-id";
snps,fixed-burst;
snps,axi-config = <&gmac1_stmmac_axi_setup>;
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
ext_rgmii_phy_1: ethernet-phy@1 {
reg = <1>;
};
};
};
...

View File

@ -62,6 +62,13 @@ properties:
- const: stmmaceth
- const: ptp_ref
interrupts:
maxItems: 1
interrupt-names:
items:
- const: macirq
iommus:
minItems: 1
maxItems: 2

View File

@ -0,0 +1,115 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/apm,xgene-enet.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: APM X-Gene SoC Ethernet
maintainers:
- Iyappan Subramanian <iyappan@os.amperecomputing.com>
- Keyur Chudgar <keyur@os.amperecomputing.com>
- Quan Nguyen <quan@os.amperecomputing.com>
allOf:
- $ref: ethernet-controller.yaml#
properties:
compatible:
enum:
- apm,xgene-enet
- apm,xgene1-sgenet
- apm,xgene1-xgenet
- apm,xgene2-sgenet
- apm,xgene2-xgenet
reg:
maxItems: 3
reg-names:
items:
- const: enet_csr
- const: ring_csr
- const: ring_cmd
clocks:
maxItems: 1
dma-coherent: true
interrupts:
description: An rx and tx completion interrupt pair per queue
minItems: 1
maxItems: 16
channel:
description: Ethernet to CPU start channel number
$ref: /schemas/types.yaml#/definitions/uint32
port-id:
description: Port number
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 1
tx-delay:
description: Delay value for RGMII bridge TX clock
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 7
default: 4
rx-delay:
description: Delay value for RGMII bridge RX clock
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 7
default: 2
rxlos-gpios:
description: Input GPIO from SFP+ module indicating incoming signal
maxItems: 1
mdio:
description: MDIO bus subnode
$ref: mdio.yaml#
unevaluatedProperties: false
properties:
compatible:
const: apm,xgene-mdio
required:
- compatible
required:
- compatible
- reg
- interrupts
unevaluatedProperties: false
examples:
- |
ethernet@17020000 {
compatible = "apm,xgene-enet";
reg = <0x17020000 0xd100>,
<0x17030000 0x400>,
<0x10000000 0x200>;
reg-names = "enet_csr", "ring_csr", "ring_cmd";
interrupts = <0x0 0x3c 0x4>;
channel = <0>;
port-id = <0>;
clocks = <&menetclk 0>;
local-mac-address = [00 01 73 00 00 01];
phy-connection-type = "rgmii";
phy-handle = <&menetphy>;
mdio {
compatible = "apm,xgene-mdio";
#address-cells = <1>;
#size-cells = <0>;
menetphy: ethernet-phy@3 {
compatible = "ethernet-phy-id001c.c915";
reg = <3>;
};
};
};

View File

@ -0,0 +1,54 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/apm,xgene-mdio-rgmii.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: APM X-Gene SoC MDIO
maintainers:
- Iyappan Subramanian <iyappan@os.amperecomputing.com>
- Keyur Chudgar <keyur@os.amperecomputing.com>
- Quan Nguyen <quan@os.amperecomputing.com>
allOf:
- $ref: mdio.yaml#
properties:
compatible:
enum:
- apm,xgene-mdio-rgmii
- apm,xgene-mdio-xfi
reg:
maxItems: 1
clocks:
maxItems: 1
unevaluatedProperties: false
required:
- compatible
- reg
- clocks
examples:
- |
mdio@17020000 {
compatible = "apm,xgene-mdio-rgmii";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x17020000 0xd100>;
clocks = <&menetclk 0>;
phy@3 {
reg = <0x3>;
};
phy@4 {
reg = <0x4>;
};
phy@5 {
reg = <0x5>;
};
};

View File

@ -1,91 +0,0 @@
APM X-Gene SoC Ethernet nodes
Ethernet nodes are defined to describe on-chip ethernet interfaces in
APM X-Gene SoC.
Required properties for all the ethernet interfaces:
- compatible: Should state binding information from the following list,
- "apm,xgene-enet": RGMII based 1G interface
- "apm,xgene1-sgenet": SGMII based 1G interface
- "apm,xgene1-xgenet": XFI based 10G interface
- reg: Address and length of the register set for the device. It contains the
information of registers in the same order as described by reg-names
- reg-names: Should contain the register set names
- "enet_csr": Ethernet control and status register address space
- "ring_csr": Descriptor ring control and status register address space
- "ring_cmd": Descriptor ring command register address space
- interrupts: Two interrupt specifiers can be specified.
- First is the Rx interrupt. This irq is mandatory.
- Second is the Tx completion interrupt.
This is supported only on SGMII based 1GbE and 10GbE interfaces.
- channel: Ethernet to CPU, start channel (prefetch buffer) number
- Must map to the first irq and irqs must be sequential
- port-id: Port number (0 or 1)
- clocks: Reference to the clock entry.
- local-mac-address: MAC address assigned to this device
- phy-connection-type: Interface type between ethernet device and PHY device
Required properties for ethernet interfaces that have external PHY:
- phy-handle: Reference to a PHY node connected to this device
- mdio: Device tree subnode with the following required properties:
- compatible: Must be "apm,xgene-mdio".
- #address-cells: Must be <1>.
- #size-cells: Must be <0>.
For the phy on the mdio bus, there must be a node with the following fields:
- compatible: PHY identifier. Please refer ./phy.txt for the format.
- reg: The ID number for the phy.
Optional properties:
- status: Should be "ok" or "disabled" for enabled/disabled. Default is "ok".
- tx-delay: Delay value for RGMII bridge TX clock.
Valid values are between 0 to 7, that maps to
417, 717, 1020, 1321, 1611, 1913, 2215, 2514 ps
Default value is 4, which corresponds to 1611 ps
- rx-delay: Delay value for RGMII bridge RX clock.
Valid values are between 0 to 7, that maps to
273, 589, 899, 1222, 1480, 1806, 2147, 2464 ps
Default value is 2, which corresponds to 899 ps
- rxlos-gpios: Input gpio from SFP+ module to indicate availability of
incoming signal.
Example:
menetclk: menetclk {
compatible = "apm,xgene-device-clock";
clock-output-names = "menetclk";
status = "ok";
};
menet: ethernet@17020000 {
compatible = "apm,xgene-enet";
status = "disabled";
reg = <0x0 0x17020000 0x0 0xd100>,
<0x0 0x17030000 0x0 0x400>,
<0x0 0x10000000 0x0 0x200>;
reg-names = "enet_csr", "ring_csr", "ring_cmd";
interrupts = <0x0 0x3c 0x4>;
port-id = <0>;
clocks = <&menetclk 0>;
local-mac-address = [00 01 73 00 00 01];
phy-connection-type = "rgmii";
phy-handle = <&menetphy>;
mdio {
compatible = "apm,xgene-mdio";
#address-cells = <1>;
#size-cells = <0>;
menetphy: menetphy@3 {
compatible = "ethernet-phy-id001c.c915";
reg = <0x3>;
};
};
};
/* Board-specific peripheral configurations */
&menet {
tx-delay = <4>;
rx-delay = <2>;
status = "ok";
};

View File

@ -1,37 +0,0 @@
APM X-Gene SoC MDIO node
MDIO node is defined to describe on-chip MDIO controller.
Required properties:
- compatible: Must be "apm,xgene-mdio-rgmii" or "apm,xgene-mdio-xfi"
- #address-cells: Must be <1>.
- #size-cells: Must be <0>.
- reg: Address and length of the register set
- clocks: Reference to the clock entry
For the phys on the mdio bus, there must be a node with the following fields:
- compatible: PHY identifier. Please refer ./phy.txt for the format.
- reg: The ID number for the phy.
Example:
mdio: mdio@17020000 {
compatible = "apm,xgene-mdio-rgmii";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x17020000 0x0 0xd100>;
clocks = <&menetclk 0>;
};
/* Board-specific peripheral configurations */
&mdio {
menetphy: phy@3 {
reg = <0x3>;
};
sgenet0phy: phy@4 {
reg = <0x4>;
};
sgenet1phy: phy@5 {
reg = <0x5>;
};
};

View File

@ -1,50 +0,0 @@
* Broadcom Starfighter 2 integrated switch
See dsa/brcm,bcm7445-switch-v4.0.yaml for the documentation.
*Deprecated* binding required properties:
- dsa,mii-bus: phandle to the MDIO bus controller, see dsa/dsa.txt
- dsa,ethernet: phandle to the CPU network interface controller, see dsa/dsa.txt
- #address-cells: must be 2, see dsa/dsa.txt
Example using the old DSA DeviceTree binding:
switch_top@f0b00000 {
compatible = "simple-bus";
#size-cells = <1>;
#address-cells = <1>;
ranges = <0 0xf0b00000 0x40804>;
ethernet_switch@0 {
compatible = "brcm,bcm7445-switch-v4.0";
#size-cells = <0>;
#address-cells = <2>;
reg = <0x0 0x40000
0x40000 0x110
0x40340 0x30
0x40380 0x30
0x40400 0x34
0x40600 0x208>;
interrupts = <0 0x18 0
0 0x19 0>;
brcm,num-gphy = <1>;
brcm,num-rgmii-ports = <2>;
brcm,fcb-pause-override;
brcm,acb-packets-inflight;
...
switch@0 {
reg = <0 0>;
#size-cells = <0>;
#address-cells = <1>;
port@0 {
label = "gphy";
reg = <0>;
brcm,use-bcm-hdr;
};
...
};
};
};

View File

@ -54,6 +54,7 @@ properties:
- cdns,np4-macb # NP4 SoC devices
- microchip,sama7g5-emac # Microchip SAMA7G5 ethernet interface
- microchip,sama7g5-gem # Microchip SAMA7G5 gigabit ethernet interface
- raspberrypi,rp1-gem # Raspberry Pi RP1 gigabit ethernet interface
- sifive,fu540-c000-gem # SiFive FU540-C000 SoC
- cdns,emac # Generic
- cdns,gem # Generic
@ -85,7 +86,7 @@ properties:
items:
- enum: [ ether_clk, hclk, pclk ]
- enum: [ hclk, pclk ]
- const: tx_clk
- enum: [ tx_clk, tsu_clk ]
- enum: [ rx_clk, tsu_clk ]
- const: tsu_clk

View File

@ -10,9 +10,6 @@ maintainers:
- Marek Vasut <marex@denx.de>
- Woojung Huh <Woojung.Huh@microchip.com>
allOf:
- $ref: /schemas/spi/spi-peripheral-props.yaml#
properties:
# See Documentation/devicetree/bindings/net/dsa/dsa.yaml for a list of additional
# required and optional properties.
@ -37,6 +34,13 @@ properties:
- microchip,ksz8567
- microchip,lan9646
pinctrl-names:
items:
- const: default
- const: reset
description:
Used during reset for strap configuration.
reset-gpios:
description:
Should be a gpio specifier for a reset line.
@ -107,38 +111,53 @@ required:
- compatible
- reg
if:
not:
properties:
compatible:
enum:
- microchip,ksz8863
- microchip,ksz8873
then:
$ref: dsa.yaml#/$defs/ethernet-ports
else:
patternProperties:
"^(ethernet-)?ports$":
allOf:
- $ref: /schemas/spi/spi-peripheral-props.yaml#
- if:
not:
properties:
compatible:
enum:
- microchip,ksz8863
- microchip,ksz8873
then:
$ref: dsa.yaml#/$defs/ethernet-ports
else:
patternProperties:
"^(ethernet-)?port@[0-2]$":
$ref: dsa-port.yaml#
unevaluatedProperties: false
properties:
microchip,rmii-clk-internal:
$ref: /schemas/types.yaml#/definitions/flag
description:
When ksz88x3 is acting as clock provier (via REFCLKO) it
can select between internal and external RMII reference
clock. Internal reference clock means that the clock for
the RMII of ksz88x3 is provided by the ksz88x3 internally
and the REFCLKI pin is unconnected. For the external
reference clock, the clock needs to be fed back to ksz88x3
via REFCLKI.
If microchip,rmii-clk-internal is set, ksz88x3 will provide
rmii reference clock internally, otherwise reference clock
should be provided externally.
dependencies:
microchip,rmii-clk-internal: [ethernet]
"^(ethernet-)?ports$":
patternProperties:
"^(ethernet-)?port@[0-2]$":
$ref: dsa-port.yaml#
unevaluatedProperties: false
properties:
microchip,rmii-clk-internal:
$ref: /schemas/types.yaml#/definitions/flag
description:
When ksz88x3 is acting as clock provier (via REFCLKO) it
can select between internal and external RMII reference
clock. Internal reference clock means that the clock for
the RMII of ksz88x3 is provided by the ksz88x3 internally
and the REFCLKI pin is unconnected. For the external
reference clock, the clock needs to be fed back to ksz88x3
via REFCLKI.
If microchip,rmii-clk-internal is set, ksz88x3 will provide
rmii reference clock internally, otherwise reference clock
should be provided externally.
dependencies:
microchip,rmii-clk-internal: [ethernet]
- if:
properties:
compatible:
contains:
const: microchip,ksz8463
then:
properties:
straps-rxd-gpios:
description:
RXD0 and RXD1 pins, used to select SPI as bus interface.
minItems: 2
maxItems: 2
unevaluatedProperties: false

View File

@ -32,6 +32,15 @@ properties:
reg:
maxItems: 1
reset-gpios:
description:
A GPIO connected to the active-low RST_N pin of the SJA1105. Note that
reset of this chip is performed via SPI and the RST_N pin must be wired
to satisfy the power-up sequence documented in "SJA1105PQRS Application
Hints" (AH1704) sec. 2.4.4. Connecting the SJA1105 RST_N pin to a GPIO is
therefore discouraged.
maxItems: 1
spi-cpha: true
spi-cpol: true

View File

@ -108,6 +108,11 @@ properties:
$ref: "#/properties/phy-handle"
deprecated: true
ptp-timer:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Specifies a reference to a node representing an IEEE 1588 PTP device.
rx-fifo-depth:
$ref: /schemas/types.yaml#/definitions/uint32
description:
@ -274,7 +279,7 @@ additionalProperties: true
# specified.
#
# One option is to make the clock traces on the PCB longer than the
# data traces. A sufficiently difference in length can provide the 2ns
# data traces. A sufficient difference in length can provide the 2ns
# delay. If both the RX and TX delays are implemented in this manner,
# 'rgmii' should be used, so indicating the PCB adds the delays.
#

View File

@ -81,10 +81,6 @@ properties:
An array of two references: the first is the FMan RX port and the second
is the TX port used by this MAC.
ptp-timer:
$ref: /schemas/types.yaml#/definitions/phandle
description: A reference to the IEEE1588 timer
phys:
description: A reference to the SerDes lane(s)
maxItems: 1

View File

@ -86,14 +86,12 @@ examples:
phy-handle = <&eth_phy>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
eth_phy: ethernet-phy@0 {
reg = <0>;
};
eth_phy: ethernet-phy@0 {
reg = <0>;
};
};
};
...
# vim: set ts=2 sw=2 sts=2 tw=80 et cc=80 ft=yaml :

View File

@ -55,12 +55,14 @@ properties:
- const: microchip,lan9691-switch
reg:
minItems: 2
items:
- description: cpu target
- description: devices target
- description: general control block target
reg-names:
minItems: 2
items:
- const: cpu
- const: devices
@ -168,6 +170,26 @@ required:
- interrupt-names
- ethernet-ports
allOf:
- if:
properties:
compatible:
contains:
enum:
- microchip,lan9691-switch
then:
properties:
reg:
minItems: 2
reg-names:
minItems: 2
else:
properties:
reg:
minItems: 3
reg-names:
minItems: 3
additionalProperties: false
examples:
@ -245,4 +267,3 @@ examples:
};
...
# vim: set ts=2 sw=2 sts=2 tw=80 et cc=80 ft=yaml :

View File

@ -56,10 +56,10 @@ properties:
Regulator for supply voltage to VIN pin
ti,rx-gain-reduction-db:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Specify an RX gain reduction to reduce antenna sensitivity with 5dB per
increment, with a maximum of 15dB. Supported values: [0, 5, 10, 15].
increment, with a maximum of 15dB.
enum: [ 0, 5, 10, 15]
required:
- compatible

View File

@ -4,14 +4,15 @@
$id: http://devicetree.org/schemas/net/pcs/renesas,rzn1-miic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas RZ/N1 MII converter
title: Renesas RZ/N1, RZ/N2H and RZ/T2H MII converter
maintainers:
- Clément Léger <clement.leger@bootlin.com>
- Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
description: |
This MII converter is present on the Renesas RZ/N1 SoC family. It is
responsible to do MII passthrough or convert it to RMII/RGMII.
This MII converter is present on the Renesas RZ/N1, RZ/N2H and RZ/T2H SoC
families. It is responsible to do MII passthrough or convert it to RMII/RGMII.
properties:
'#address-cells':
@ -21,10 +22,16 @@ properties:
const: 0
compatible:
items:
- enum:
- renesas,r9a06g032-miic
- const: renesas,rzn1-miic
oneOf:
- items:
- enum:
- renesas,r9a06g032-miic
- const: renesas,rzn1-miic
- items:
- const: renesas,r9a09g077-miic # RZ/T2H
- items:
- const: renesas,r9a09g087-miic # RZ/N2H
- const: renesas,r9a09g077-miic
reg:
maxItems: 1
@ -43,11 +50,22 @@ properties:
- const: rmii_ref
- const: hclk
resets:
items:
- description: Converter register reset
- description: Converter reset
reset-names:
items:
- const: rst
- const: crst
renesas,miic-switch-portin:
description: MII Switch PORTIN configuration. This value should use one of
the values defined in dt-bindings/net/pcs-rzn1-miic.h.
the values defined in dt-bindings/net/pcs-rzn1-miic.h for RZ/N1 SoC and
include/dt-bindings/net/renesas,r9a09g077-pcs-miic.h for RZ/N2H, RZ/T2H SoCs.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [1, 2]
enum: [0, 1, 2]
power-domains:
maxItems: 1
@ -60,11 +78,12 @@ patternProperties:
properties:
reg:
description: MII Converter port number.
enum: [1, 2, 3, 4, 5]
enum: [0, 1, 2, 3, 4, 5]
renesas,miic-input:
description: Converter input port configuration. This value should use
one of the values defined in dt-bindings/net/pcs-rzn1-miic.h.
one of the values defined in dt-bindings/net/pcs-rzn1-miic.h for RZ/N1 SoC
and include/dt-bindings/net/renesas,r9a09g077-pcs-miic.h for RZ/N2H, RZ/T2H SoCs.
$ref: /schemas/types.yaml#/definitions/uint32
required:
@ -73,47 +92,109 @@ patternProperties:
additionalProperties: false
allOf:
- if:
allOf:
- if:
properties:
compatible:
contains:
const: renesas,rzn1-miic
then:
properties:
renesas,miic-switch-portin:
enum: [1, 2]
resets: false
reset-names: false
patternProperties:
"^mii-conv@[0-5]$":
properties:
reg:
const: 1
then:
properties:
renesas,miic-input:
const: 0
- if:
enum: [1, 2, 3, 4, 5]
allOf:
- if:
properties:
reg:
const: 1
then:
properties:
renesas,miic-input:
const: 0
- if:
properties:
reg:
const: 2
then:
properties:
renesas,miic-input:
enum: [1, 11]
- if:
properties:
reg:
const: 3
then:
properties:
renesas,miic-input:
enum: [7, 10]
- if:
properties:
reg:
const: 4
then:
properties:
renesas,miic-input:
enum: [4, 6, 9, 13]
- if:
properties:
reg:
const: 5
then:
properties:
renesas,miic-input:
enum: [3, 5, 8, 12]
else:
properties:
renesas,miic-switch-portin:
const: 0
required:
- resets
- reset-names
patternProperties:
"^mii-conv@[0-5]$":
properties:
reg:
const: 2
then:
properties:
renesas,miic-input:
enum: [1, 11]
- if:
properties:
reg:
const: 3
then:
properties:
renesas,miic-input:
enum: [7, 10]
- if:
properties:
reg:
const: 4
then:
properties:
renesas,miic-input:
enum: [4, 6, 9, 13]
- if:
properties:
reg:
const: 5
then:
properties:
renesas,miic-input:
enum: [3, 5, 8, 12]
enum: [0, 1, 2, 3]
allOf:
- if:
properties:
reg:
const: 0
then:
properties:
renesas,miic-input:
enum: [0, 3, 6]
- if:
properties:
reg:
const: 1
then:
properties:
renesas,miic-input:
enum: [1, 4, 7]
- if:
properties:
reg:
const: 2
then:
properties:
renesas,miic-input:
enum: [2, 5, 8]
- if:
properties:
reg:
const: 3
then:
properties:
renesas,miic-input:
const: 1
required:
- '#address-cells'

View File

@ -0,0 +1,144 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/pse-pd/skyworks,si3474.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Skyworks Si3474 Power Sourcing Equipment controller
maintainers:
- Piotr Kubik <piotr.kubik@adtran.com>
allOf:
- $ref: pse-controller.yaml#
properties:
compatible:
enum:
- skyworks,si3474
reg:
maxItems: 2
reg-names:
items:
- const: main
- const: secondary
channels:
description: The Si3474 is a single-chip PoE PSE controller managing
8 physical power delivery channels. Internally, it's structured
into two logical "Quads".
Quad 0 Manages physical channels ('ports' in datasheet) 0, 1, 2, 3
Quad 1 Manages physical channels ('ports' in datasheet) 4, 5, 6, 7.
type: object
additionalProperties: false
properties:
"#address-cells":
const: 1
"#size-cells":
const: 0
patternProperties:
'^channel@[0-7]$':
type: object
additionalProperties: false
properties:
reg:
maxItems: 1
required:
- reg
required:
- "#address-cells"
- "#size-cells"
required:
- compatible
- reg
- pse-pis
unevaluatedProperties: false
examples:
- |
i2c {
#address-cells = <1>;
#size-cells = <0>;
ethernet-pse@26 {
compatible = "skyworks,si3474";
reg-names = "main", "secondary";
reg = <0x26>, <0x27>;
channels {
#address-cells = <1>;
#size-cells = <0>;
phys0_0: channel@0 {
reg = <0>;
};
phys0_1: channel@1 {
reg = <1>;
};
phys0_2: channel@2 {
reg = <2>;
};
phys0_3: channel@3 {
reg = <3>;
};
phys0_4: channel@4 {
reg = <4>;
};
phys0_5: channel@5 {
reg = <5>;
};
phys0_6: channel@6 {
reg = <6>;
};
phys0_7: channel@7 {
reg = <7>;
};
};
pse-pis {
#address-cells = <1>;
#size-cells = <0>;
pse_pi0: pse-pi@0 {
reg = <0>;
#pse-cells = <0>;
pairset-names = "alternative-a", "alternative-b";
pairsets = <&phys0_0>, <&phys0_1>;
polarity-supported = "MDI-X", "S";
vpwr-supply = <&reg_pse>;
};
pse_pi1: pse-pi@1 {
reg = <1>;
#pse-cells = <0>;
pairset-names = "alternative-a", "alternative-b";
pairsets = <&phys0_2>, <&phys0_3>;
polarity-supported = "MDI-X", "S";
vpwr-supply = <&reg_pse>;
};
pse_pi2: pse-pi@2 {
reg = <2>;
#pse-cells = <0>;
pairset-names = "alternative-a", "alternative-b";
pairsets = <&phys0_4>, <&phys0_5>;
polarity-supported = "MDI-X", "S";
vpwr-supply = <&reg_pse>;
};
pse_pi3: pse-pi@3 {
reg = <3>;
#pse-cells = <0>;
pairset-names = "alternative-a", "alternative-b";
pairsets = <&phys0_6>, <&phys0_7>;
polarity-supported = "MDI-X", "S";
vpwr-supply = <&reg_pse>;
};
};
};
};

View File

@ -0,0 +1,533 @@
# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/qcom,ipq9574-ppe.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm IPQ packet process engine (PPE)
maintainers:
- Luo Jie <quic_luoj@quicinc.com>
- Lei Wei <quic_leiwei@quicinc.com>
- Suruchi Agarwal <quic_suruchia@quicinc.com>
- Pavithra R <quic_pavir@quicinc.com>
description: |
The Ethernet functionality in the PPE (Packet Process Engine) is comprised
of three components, the switch core, port wrapper and Ethernet DMA.
The Switch core in the IPQ9574 PPE has maximum of 6 front panel ports and
two FIFO interfaces. One of the two FIFO interfaces is used for Ethernet
port to host CPU communication using Ethernet DMA. The other is used
communicating to the EIP engine which is used for IPsec offload. On the
IPQ9574, the PPE includes 6 GMAC/XGMACs that can be connected with external
Ethernet PHY. Switch core also includes BM (Buffer Management), QM (Queue
Management) and SCH (Scheduler) modules for supporting the packet processing.
The port wrapper provides connections from the 6 GMAC/XGMACS to UNIPHY (PCS)
supporting various modes such as SGMII/QSGMII/PSGMII/USXGMII/10G-BASER. There
are 3 UNIPHY (PCS) instances supported on the IPQ9574.
Ethernet DMA is used to transmit and receive packets between the six Ethernet
ports and ARM host CPU.
The follow diagram shows the PPE hardware block along with its connectivity
to the external hardware blocks such clock hardware blocks (CMNPLL, GCC,
NSS clock controller) and Ethernet PCS/PHY blocks. For depicting the PHY
connectivity, one 4x1 Gbps PHY (QCA8075) and two 10 GBps PHYs are used as an
example.
+---------+
| 48 MHZ |
+----+----+
|(clock)
v
+----+----+
+------| CMN PLL |
| +----+----+
| |(clock)
| v
| +----+----+ +----+----+ (clock) +----+----+
| +---| NSSCC | | GCC |--------->| MDIO |
| | +----+----+ +----+----+ +----+----+
| | |(clock & reset) |(clock)
| | v v
| | +----+---------------------+--+----------+----------+---------+
| | | +-----+ |EDMA FIFO | | EIP FIFO|
| | | | SCH | +----------+ +---------+
| | | +-----+ | | |
| | | +------+ +------+ +-------------------+ |
| | | | BM | | QM | IPQ9574-PPE | L2/L3 Process | |
| | | +------+ +------+ +-------------------+ |
| | | | |
| | | +-------+ +-------+ +-------+ +-------+ +-------+ +-------+ |
| | | | MAC0 | | MAC1 | | MAC2 | | MAC3 | | XGMAC4| |XGMAC5 | |
| | | +---+---+ +---+---+ +---+---+ +---+---+ +---+---+ +---+---+ |
| | | | | | | | | |
| | +-----+---------+---------+---------+---------+---------+-----+
| | | | | | | |
| | +---+---------+---------+---------+---+ +---+---+ +---+---+
+--+---->| PCS0 | | PCS1 | | PCS2 |
|(clock) +---+---------+---------+---------+---+ +---+---+ +---+---+
| | | | | | |
| +---+---------+---------+---------+---+ +---+---+ +---+---+
+------->| QCA8075 PHY | | PHY4 | | PHY5 |
(clock) +-------------------------------------+ +-------+ +-------+
properties:
compatible:
enum:
- qcom,ipq9574-ppe
reg:
maxItems: 1
clocks:
items:
- description: PPE core clock
- description: PPE APB (Advanced Peripheral Bus) clock
- description: PPE IPE (Ingress Process Engine) clock
- description: PPE BM, QM and scheduler clock
clock-names:
items:
- const: ppe
- const: apb
- const: ipe
- const: btq
resets:
maxItems: 1
description: PPE reset, which is necessary before configuring PPE hardware
interrupts:
maxItems: 1
description: PPE switch miscellaneous interrupt
interconnects:
items:
- description: Bus interconnect path leading to PPE switch core function
- description: Bus interconnect path leading to PPE register access
- description: Bus interconnect path leading to QoS generation
- description: Bus interconnect path leading to timeout reference
- description: Bus interconnect path leading to NSS NOC from memory NOC
- description: Bus interconnect path leading to memory NOC from NSS NOC
- description: Bus interconnect path leading to enhanced memory NOC from NSS NOC
interconnect-names:
items:
- const: ppe
- const: ppe_cfg
- const: qos_gen
- const: timeout_ref
- const: nssnoc_memnoc
- const: memnoc_nssnoc
- const: memnoc_nssnoc_1
ethernet-dma:
type: object
additionalProperties: false
description:
EDMA (Ethernet DMA) is used to transmit packets between PPE and ARM
host CPU. There are 32 TX descriptor rings, 32 TX completion rings,
24 RX descriptor rings and 8 RX fill rings supported.
properties:
clocks:
items:
- description: EDMA system clock
- description: EDMA APB (Advanced Peripheral Bus) clock
clock-names:
items:
- const: sys
- const: apb
resets:
maxItems: 1
description: EDMA reset
interrupts:
minItems: 65
maxItems: 65
interrupt-names:
minItems: 65
maxItems: 65
items:
oneOf:
- pattern: '^txcmpl_([1-2]?[0-9]|3[01])$'
- pattern: '^rxfill_[0-7]$'
- pattern: '^rxdesc_(1?[0-9]|2[0-3])$'
- const: misc
description:
Interrupts "txcmpl_[0-31]" are the Ethernet DMA TX completion ring interrupts.
Interrupts "rxfill_[0-7]" are the Ethernet DMA RX fill ring interrupts.
Interrupts "rxdesc_[0-23]" are the Ethernet DMA RX Descriptor ring interrupts.
Interrupt "misc" is the Ethernet DMA miscellaneous error interrupt.
required:
- clocks
- clock-names
- resets
- interrupts
- interrupt-names
ethernet-ports:
patternProperties:
"^ethernet-port@[1-6]+$":
type: object
unevaluatedProperties: false
$ref: ethernet-switch-port.yaml#
properties:
reg:
minimum: 1
maximum: 6
description: PPE Ethernet port ID
clocks:
items:
- description: Port MAC clock
- description: Port RX clock
- description: Port TX clock
clock-names:
items:
- const: mac
- const: rx
- const: tx
resets:
items:
- description: Port MAC reset
- description: Port RX reset
- description: Port TX reset
reset-names:
items:
- const: mac
- const: rx
- const: tx
required:
- reg
- clocks
- clock-names
- resets
- reset-names
required:
- compatible
- reg
- clocks
- clock-names
- resets
- interconnects
- interconnect-names
- ethernet-dma
allOf:
- $ref: ethernet-switch.yaml
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,ipq9574-gcc.h>
#include <dt-bindings/clock/qcom,ipq9574-nsscc.h>
#include <dt-bindings/interconnect/qcom,ipq9574.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/qcom,ipq9574-nsscc.h>
ethernet-switch@3a000000 {
compatible = "qcom,ipq9574-ppe";
reg = <0x3a000000 0xbef800>;
clocks = <&nsscc NSS_CC_PPE_SWITCH_CLK>,
<&nsscc NSS_CC_PPE_SWITCH_CFG_CLK>,
<&nsscc NSS_CC_PPE_SWITCH_IPE_CLK>,
<&nsscc NSS_CC_PPE_SWITCH_BTQ_CLK>;
clock-names = "ppe",
"apb",
"ipe",
"btq";
resets = <&nsscc PPE_FULL_RESET>;
interrupts = <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH>;
interconnects = <&nsscc MASTER_NSSNOC_PPE &nsscc SLAVE_NSSNOC_PPE>,
<&nsscc MASTER_NSSNOC_PPE_CFG &nsscc SLAVE_NSSNOC_PPE_CFG>,
<&gcc MASTER_NSSNOC_QOSGEN_REF &gcc SLAVE_NSSNOC_QOSGEN_REF>,
<&gcc MASTER_NSSNOC_TIMEOUT_REF &gcc SLAVE_NSSNOC_TIMEOUT_REF>,
<&gcc MASTER_MEM_NOC_NSSNOC &gcc SLAVE_MEM_NOC_NSSNOC>,
<&gcc MASTER_NSSNOC_MEMNOC &gcc SLAVE_NSSNOC_MEMNOC>,
<&gcc MASTER_NSSNOC_MEM_NOC_1 &gcc SLAVE_NSSNOC_MEM_NOC_1>;
interconnect-names = "ppe",
"ppe_cfg",
"qos_gen",
"timeout_ref",
"nssnoc_memnoc",
"memnoc_nssnoc",
"memnoc_nssnoc_1";
ethernet-dma {
clocks = <&nsscc NSS_CC_PPE_EDMA_CLK>,
<&nsscc NSS_CC_PPE_EDMA_CFG_CLK>;
clock-names = "sys",
"apb";
resets = <&nsscc EDMA_HW_RESET>;
interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "txcmpl_0",
"txcmpl_1",
"txcmpl_2",
"txcmpl_3",
"txcmpl_4",
"txcmpl_5",
"txcmpl_6",
"txcmpl_7",
"txcmpl_8",
"txcmpl_9",
"txcmpl_10",
"txcmpl_11",
"txcmpl_12",
"txcmpl_13",
"txcmpl_14",
"txcmpl_15",
"txcmpl_16",
"txcmpl_17",
"txcmpl_18",
"txcmpl_19",
"txcmpl_20",
"txcmpl_21",
"txcmpl_22",
"txcmpl_23",
"txcmpl_24",
"txcmpl_25",
"txcmpl_26",
"txcmpl_27",
"txcmpl_28",
"txcmpl_29",
"txcmpl_30",
"txcmpl_31",
"rxfill_0",
"rxfill_1",
"rxfill_2",
"rxfill_3",
"rxfill_4",
"rxfill_5",
"rxfill_6",
"rxfill_7",
"rxdesc_0",
"rxdesc_1",
"rxdesc_2",
"rxdesc_3",
"rxdesc_4",
"rxdesc_5",
"rxdesc_6",
"rxdesc_7",
"rxdesc_8",
"rxdesc_9",
"rxdesc_10",
"rxdesc_11",
"rxdesc_12",
"rxdesc_13",
"rxdesc_14",
"rxdesc_15",
"rxdesc_16",
"rxdesc_17",
"rxdesc_18",
"rxdesc_19",
"rxdesc_20",
"rxdesc_21",
"rxdesc_22",
"rxdesc_23",
"misc";
};
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
ethernet-port@1 {
reg = <1>;
phy-mode = "qsgmii";
managed = "in-band-status";
phy-handle = <&phy0>;
pcs-handle = <&pcs0_ch0>;
clocks = <&nsscc NSS_CC_PORT1_MAC_CLK>,
<&nsscc NSS_CC_PORT1_RX_CLK>,
<&nsscc NSS_CC_PORT1_TX_CLK>;
clock-names = "mac",
"rx",
"tx";
resets = <&nsscc PORT1_MAC_ARES>,
<&nsscc PORT1_RX_ARES>,
<&nsscc PORT1_TX_ARES>;
reset-names = "mac",
"rx",
"tx";
};
ethernet-port@2 {
reg = <2>;
phy-mode = "qsgmii";
managed = "in-band-status";
phy-handle = <&phy1>;
pcs-handle = <&pcs0_ch1>;
clocks = <&nsscc NSS_CC_PORT2_MAC_CLK>,
<&nsscc NSS_CC_PORT2_RX_CLK>,
<&nsscc NSS_CC_PORT2_TX_CLK>;
clock-names = "mac",
"rx",
"tx";
resets = <&nsscc PORT2_MAC_ARES>,
<&nsscc PORT2_RX_ARES>,
<&nsscc PORT2_TX_ARES>;
reset-names = "mac",
"rx",
"tx";
};
ethernet-port@3 {
reg = <3>;
phy-mode = "qsgmii";
managed = "in-band-status";
phy-handle = <&phy2>;
pcs-handle = <&pcs0_ch2>;
clocks = <&nsscc NSS_CC_PORT3_MAC_CLK>,
<&nsscc NSS_CC_PORT3_RX_CLK>,
<&nsscc NSS_CC_PORT3_TX_CLK>;
clock-names = "mac",
"rx",
"tx";
resets = <&nsscc PORT3_MAC_ARES>,
<&nsscc PORT3_RX_ARES>,
<&nsscc PORT3_TX_ARES>;
reset-names = "mac",
"rx",
"tx";
};
ethernet-port@4 {
reg = <4>;
phy-mode = "qsgmii";
managed = "in-band-status";
phy-handle = <&phy3>;
pcs-handle = <&pcs0_ch3>;
clocks = <&nsscc NSS_CC_PORT4_MAC_CLK>,
<&nsscc NSS_CC_PORT4_RX_CLK>,
<&nsscc NSS_CC_PORT4_TX_CLK>;
clock-names = "mac",
"rx",
"tx";
resets = <&nsscc PORT4_MAC_ARES>,
<&nsscc PORT4_RX_ARES>,
<&nsscc PORT4_TX_ARES>;
reset-names = "mac",
"rx",
"tx";
};
ethernet-port@5 {
reg = <5>;
phy-mode = "usxgmii";
managed = "in-band-status";
phy-handle = <&phy4>;
pcs-handle = <&pcs1_ch0>;
clocks = <&nsscc NSS_CC_PORT5_MAC_CLK>,
<&nsscc NSS_CC_PORT5_RX_CLK>,
<&nsscc NSS_CC_PORT5_TX_CLK>;
clock-names = "mac",
"rx",
"tx";
resets = <&nsscc PORT5_MAC_ARES>,
<&nsscc PORT5_RX_ARES>,
<&nsscc PORT5_TX_ARES>;
reset-names = "mac",
"rx",
"tx";
};
ethernet-port@6 {
reg = <6>;
phy-mode = "usxgmii";
managed = "in-band-status";
phy-handle = <&phy5>;
pcs-handle = <&pcs2_ch0>;
clocks = <&nsscc NSS_CC_PORT6_MAC_CLK>,
<&nsscc NSS_CC_PORT6_RX_CLK>,
<&nsscc NSS_CC_PORT6_TX_CLK>;
clock-names = "mac",
"rx",
"tx";
resets = <&nsscc PORT6_MAC_ARES>,
<&nsscc PORT6_RX_ARES>,
<&nsscc PORT6_TX_ARES>;
reset-names = "mac",
"rx",
"tx";
};
};
};

View File

@ -45,12 +45,16 @@ properties:
description:
Disable CLKOUT clock, CLKOUT clock default is enabled after hardware reset.
realtek,aldps-enable:
type: boolean
description:
Enable ALDPS mode, ALDPS mode default is disabled after hardware reset.
wakeup-source:
type: boolean
description:
Enable Wake-on-LAN support for the RTL8211F PHY.
unevaluatedProperties: false
allOf:

View File

@ -30,6 +30,15 @@ properties:
- const: renesas,rzn1-gmac
- const: snps,dwmac
interrupts:
maxItems: 3
interrupt-names:
items:
- const: macirq
- const: eth_wake_irq
- const: eth_lpi
pcs-handle:
description:
phandle pointing to a PCS sub-node compatible with

View File

@ -17,63 +17,111 @@ select:
- renesas,r9a09g047-gbeth
- renesas,r9a09g056-gbeth
- renesas,r9a09g057-gbeth
- renesas,r9a09g077-gbeth
- renesas,r9a09g087-gbeth
- renesas,rzv2h-gbeth
required:
- compatible
properties:
compatible:
items:
- enum:
- renesas,r9a09g047-gbeth # RZ/G3E
- renesas,r9a09g056-gbeth # RZ/V2N
- renesas,r9a09g057-gbeth # RZ/V2H(P)
- const: renesas,rzv2h-gbeth
- const: snps,dwmac-5.20
oneOf:
- items:
- enum:
- renesas,r9a09g047-gbeth # RZ/G3E
- renesas,r9a09g056-gbeth # RZ/V2N
- renesas,r9a09g057-gbeth # RZ/V2H(P)
- const: renesas,rzv2h-gbeth
- const: snps,dwmac-5.20
- items:
- const: renesas,r9a09g077-gbeth # RZ/T2H
- const: snps,dwmac-5.20
- items:
- const: renesas,r9a09g087-gbeth # RZ/N2H
- const: renesas,r9a09g077-gbeth
- const: snps,dwmac-5.20
reg:
maxItems: 1
clocks:
items:
- description: CSR clock
- description: AXI system clock
- description: PTP clock
- description: TX clock
- description: RX clock
- description: TX clock phase-shifted by 180 degrees
- description: RX clock phase-shifted by 180 degrees
oneOf:
- items:
- description: CSR clock
- description: AXI system clock
- description: PTP clock
- description: TX clock
- description: RX clock
- description: TX clock phase-shifted by 180 degrees
- description: RX clock phase-shifted by 180 degrees
- items:
- description: CSR clock
- description: AXI system clock
- description: TX clock
clock-names:
items:
- const: stmmaceth
- const: pclk
- const: ptp_ref
- const: tx
- const: rx
- const: tx-180
- const: rx-180
interrupts:
minItems: 11
oneOf:
- items:
- const: stmmaceth
- const: pclk
- const: ptp_ref
- const: tx
- const: rx
- const: tx-180
- const: rx-180
- items:
- const: stmmaceth
- const: pclk
- const: tx
interrupt-names:
items:
- const: macirq
- const: eth_wake_irq
- const: eth_lpi
- const: rx-queue-0
- const: rx-queue-1
- const: rx-queue-2
- const: rx-queue-3
- const: tx-queue-0
- const: tx-queue-1
- const: tx-queue-2
- const: tx-queue-3
oneOf:
- items:
- const: macirq
- const: eth_wake_irq
- const: eth_lpi
- const: rx-queue-0
- const: rx-queue-1
- const: rx-queue-2
- const: rx-queue-3
- const: tx-queue-0
- const: tx-queue-1
- const: tx-queue-2
- const: tx-queue-3
- items:
- const: macirq
- const: eth_wake_irq
- const: eth_lpi
- const: rx-queue-0
- const: rx-queue-1
- const: rx-queue-2
- const: rx-queue-3
- const: rx-queue-4
- const: rx-queue-5
- const: rx-queue-6
- const: rx-queue-7
- const: tx-queue-0
- const: tx-queue-1
- const: tx-queue-2
- const: tx-queue-3
- const: tx-queue-4
- const: tx-queue-5
- const: tx-queue-6
- const: tx-queue-7
resets:
items:
- description: AXI power-on system reset
oneOf:
- items:
- description: AXI power-on system reset
- items:
- description: AXI power-on system reset
- description: AHB reset
pcs-handle:
description:
phandle pointing to a PCS sub-node compatible with
Documentation/devicetree/bindings/net/pcs/renesas,rzn1-miic.yaml#
(Refer RZ/T2H portion in the DT-binding file)
required:
- compatible
@ -87,6 +135,56 @@ required:
allOf:
- $ref: snps,dwmac.yaml#
- if:
properties:
compatible:
contains:
const: renesas,r9a09g077-gbeth
then:
properties:
clocks:
maxItems: 3
clock-names:
maxItems: 3
interrupts:
minItems: 19
interrupt-names:
minItems: 19
resets:
minItems: 2
reset-names:
minItems: 2
required:
- reset-names
else:
properties:
clocks:
minItems: 7
clock-names:
minItems: 7
interrupts:
minItems: 11
maxItems: 11
interrupt-names:
minItems: 11
maxItems: 11
resets:
maxItems: 1
pcs-handle: false
reset-names: false
unevaluatedProperties: false
examples:

View File

@ -75,6 +75,7 @@ properties:
- qcom,sc8280xp-ethqos
- qcom,sm8150-ethqos
- renesas,r9a06g032-gmac
- renesas,r9a09g077-gbeth
- renesas,rzn1-gmac
- renesas,rzv2h-gbeth
- rockchip,px30-gmac
@ -118,11 +119,11 @@ properties:
interrupts:
minItems: 1
maxItems: 11
maxItems: 19
interrupt-names:
minItems: 1
maxItems: 11
maxItems: 19
items:
oneOf:
- description: Combined signal for various interrupt events
@ -134,9 +135,9 @@ properties:
- description: The interrupt that occurs when HW safety error triggered
const: sfty
- description: Per channel receive completion interrupt
pattern: '^rx-queue-[0-3]$'
pattern: '^rx-queue-[0-7]$'
- description: Per channel transmit completion interrupt
pattern: '^tx-queue-[0-3]$'
pattern: '^tx-queue-[0-7]$'
clocks:
minItems: 1

View File

@ -0,0 +1,81 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/spacemit,k1-emac.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: SpacemiT K1 Ethernet MAC
allOf:
- $ref: ethernet-controller.yaml#
maintainers:
- Vivian Wang <wangruikang@iscas.ac.cn>
properties:
compatible:
const: spacemit,k1-emac
reg:
maxItems: 1
clocks:
maxItems: 1
interrupts:
maxItems: 1
mdio-bus:
$ref: mdio.yaml#
unevaluatedProperties: false
resets:
maxItems: 1
spacemit,apmu:
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
- items:
- description: phandle to syscon that controls this MAC
- description: offset of control registers
description:
A phandle to syscon with byte offset to control registers for this MAC
required:
- compatible
- reg
- clocks
- interrupts
- resets
- spacemit,apmu
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/spacemit,k1-syscon.h>
ethernet@cac80000 {
compatible = "spacemit,k1-emac";
reg = <0xcac80000 0x00000420>;
clocks = <&syscon_apmu CLK_EMAC0_BUS>;
interrupts = <131>;
mac-address = [ 00 00 00 00 00 00 ];
phy-handle = <&rgmii0>;
phy-mode = "rgmii-id";
pinctrl-names = "default";
pinctrl-0 = <&gmac0_cfg>;
resets = <&syscon_apmu RESET_EMAC0>;
rx-internal-delay-ps = <0>;
tx-internal-delay-ps = <0>;
spacemit,apmu = <&syscon_apmu 0x3e4>;
mdio-bus {
#address-cells = <0x1>;
#size-cells = <0x0>;
rgmii0: phy@1 {
reg = <0x1>;
};
};
};

View File

@ -8,6 +8,8 @@ title: Texas Instruments ICSS Industrial Ethernet Peripheral (IEP) module
maintainers:
- Md Danish Anwar <danishanwar@ti.com>
- Parvathi Pudi <parvathi@couthit.com>
- Basharath Hussain Khaja <basharath@couthit.com>
properties:
compatible:
@ -17,9 +19,11 @@ properties:
- ti,am642-icss-iep
- ti,j721e-icss-iep
- const: ti,am654-icss-iep
- const: ti,am654-icss-iep
- enum:
- ti,am654-icss-iep
- ti,am5728-icss-iep
- ti,am4376-icss-iep
- ti,am3356-icss-iep
reg:
maxItems: 1

View File

@ -0,0 +1,233 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/ti,icssm-prueth.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Texas Instruments ICSSM PRUSS Ethernet
maintainers:
- Roger Quadros <rogerq@ti.com>
- Andrew F. Davis <afd@ti.com>
- Parvathi Pudi <parvathi@couthit.com>
- Basharath Hussain Khaja <basharath@couthit.com>
description:
Ethernet based on the Programmable Real-Time Unit and Industrial
Communication Subsystem.
properties:
compatible:
enum:
- ti,am57-prueth # for AM57x SoC family
- ti,am4376-prueth # for AM43x SoC family
- ti,am3359-prueth # for AM33x SoC family
sram:
$ref: /schemas/types.yaml#/definitions/phandle
description:
phandle to OCMC SRAM node
ti,mii-rt:
$ref: /schemas/types.yaml#/definitions/phandle
description:
phandle to the MII_RT peripheral for ICSS
ti,iep:
$ref: /schemas/types.yaml#/definitions/phandle
description:
phandle to IEP (Industrial Ethernet Peripheral) for ICSS
ti,ecap:
$ref: /schemas/types.yaml#/definitions/phandle
description:
phandle to Enhanced Capture (eCAP) event for ICSS
interrupts:
items:
- description: High priority Rx Interrupt specifier.
- description: Low priority Rx Interrupt specifier.
interrupt-names:
items:
- const: rx_hp
- const: rx_lp
ethernet-ports:
type: object
additionalProperties: false
properties:
'#address-cells':
const: 1
'#size-cells':
const: 0
patternProperties:
^ethernet-port@[0-1]$:
type: object
description: ICSSM PRUETH external ports
$ref: ethernet-controller.yaml#
unevaluatedProperties: false
properties:
reg:
items:
- enum: [0, 1]
description: ICSSM PRUETH port number
interrupts:
maxItems: 3
interrupt-names:
items:
- const: rx
- const: emac_ptp_tx
- const: hsr_ptp_tx
required:
- reg
anyOf:
- required:
- ethernet-port@0
- required:
- ethernet-port@1
required:
- compatible
- sram
- ti,mii-rt
- ti,iep
- ti,ecap
- ethernet-ports
- interrupts
- interrupt-names
allOf:
- $ref: /schemas/remoteproc/ti,pru-consumer.yaml#
unevaluatedProperties: false
examples:
- |
/* Dual-MAC Ethernet application node on PRU-ICSS2 */
pruss2_eth: pruss2-eth {
compatible = "ti,am57-prueth";
ti,prus = <&pru2_0>, <&pru2_1>;
sram = <&ocmcram1>;
ti,mii-rt = <&pruss2_mii_rt>;
ti,iep = <&pruss2_iep>;
ti,ecap = <&pruss2_ecap>;
interrupts = <20 2 2>, <21 3 3>;
interrupt-names = "rx_hp", "rx_lp";
interrupt-parent = <&pruss2_intc>;
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
pruss2_emac0: ethernet-port@0 {
reg = <0>;
phy-handle = <&pruss2_eth0_phy>;
phy-mode = "mii";
interrupts = <20 2 2>, <26 6 6>, <23 6 6>;
interrupt-names = "rx", "emac_ptp_tx", "hsr_ptp_tx";
/* Filled in by bootloader */
local-mac-address = [00 00 00 00 00 00];
};
pruss2_emac1: ethernet-port@1 {
reg = <1>;
phy-handle = <&pruss2_eth1_phy>;
phy-mode = "mii";
interrupts = <21 3 3>, <27 9 7>, <24 9 7>;
interrupt-names = "rx", "emac_ptp_tx", "hsr_ptp_tx";
/* Filled in by bootloader */
local-mac-address = [00 00 00 00 00 00];
};
};
};
- |
/* Dual-MAC Ethernet application node on PRU-ICSS1 */
pruss1_eth: pruss1-eth {
compatible = "ti,am4376-prueth";
ti,prus = <&pru1_0>, <&pru1_1>;
sram = <&ocmcram>;
ti,mii-rt = <&pruss1_mii_rt>;
ti,iep = <&pruss1_iep>;
ti,ecap = <&pruss1_ecap>;
interrupts = <20 2 2>, <21 3 3>;
interrupt-names = "rx_hp", "rx_lp";
interrupt-parent = <&pruss1_intc>;
pinctrl-0 = <&pruss1_eth_default>;
pinctrl-names = "default";
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
pruss1_emac0: ethernet-port@0 {
reg = <0>;
phy-handle = <&pruss1_eth0_phy>;
phy-mode = "mii";
interrupts = <20 2 2>, <26 6 6>, <23 6 6>;
interrupt-names = "rx", "emac_ptp_tx",
"hsr_ptp_tx";
/* Filled in by bootloader */
local-mac-address = [00 00 00 00 00 00];
};
pruss1_emac1: ethernet-port@1 {
reg = <1>;
phy-handle = <&pruss1_eth1_phy>;
phy-mode = "mii";
interrupts = <21 3 3>, <27 9 7>, <24 9 7>;
interrupt-names = "rx", "emac_ptp_tx",
"hsr_ptp_tx";
/* Filled in by bootloader */
local-mac-address = [00 00 00 00 00 00];
};
};
};
- |
/* Dual-MAC Ethernet application node on PRU-ICSS */
pruss_eth: pruss-eth {
compatible = "ti,am3359-prueth";
ti,prus = <&pru0>, <&pru1>;
sram = <&ocmcram>;
ti,mii-rt = <&pruss_mii_rt>;
ti,iep = <&pruss_iep>;
ti,ecap = <&pruss_ecap>;
interrupts = <20 2 2>, <21 3 3>;
interrupt-names = "rx_hp", "rx_lp";
interrupt-parent = <&pruss_intc>;
pinctrl-0 = <&pruss_eth_default>;
pinctrl-names = "default";
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
pruss_emac0: ethernet-port@0 {
reg = <0>;
phy-handle = <&pruss_eth0_phy>;
phy-mode = "mii";
interrupts = <20 2 2>, <26 6 6>, <23 6 6>;
interrupt-names = "rx", "emac_ptp_tx",
"hsr_ptp_tx";
/* Filled in by bootloader */
local-mac-address = [00 00 00 00 00 00];
};
pruss_emac1: ethernet-port@1 {
reg = <1>;
phy-handle = <&pruss_eth1_phy>;
phy-mode = "mii";
interrupts = <21 3 3>, <27 9 7>, <24 9 7>;
interrupt-names = "rx", "emac_ptp_tx",
"hsr_ptp_tx";
/* Filled in by bootloader */
local-mac-address = [00 00 00 00 00 00];
};
};
};

View File

@ -0,0 +1,32 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/ti,pruss-ecap.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Texas Instruments PRU-ICSS Enhanced Capture (eCAP) event module
maintainers:
- Murali Karicheri <m-karicheri2@ti.com>
- Parvathi Pudi <parvathi@couthit.com>
- Basharath Hussain Khaja <basharath@couthit.com>
properties:
compatible:
const: ti,pruss-ecap
reg:
maxItems: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
pruss2_ecap: ecap@30000 {
compatible = "ti,pruss-ecap";
reg = <0x30000 0x60>;
};

View File

@ -0,0 +1,63 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/ptp/nxp,ptp-netc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NXP NETC V4 Timer PTP clock
description:
NETC V4 Timer provides current time with nanosecond resolution, precise
periodic pulse, pulse on timeout (alarm), and time capture on external
pulse support. And it supports time synchronization as required for
IEEE 1588 and IEEE 802.1AS-2020.
maintainers:
- Wei Fang <wei.fang@nxp.com>
- Clark Wang <xiaoning.wang@nxp.com>
properties:
compatible:
enum:
- pci1131,ee02
reg:
maxItems: 1
clocks:
maxItems: 1
description:
The reference clock of NETC Timer, can be selected between 3 different
clock sources using an integrated hardware mux TMR_CTRL[CK_SEL].
The "ccm" means the reference clock comes from CCM of SoC.
The "ext" means the reference clock comes from external IO pins.
If not present, indicates that the system clock of NETC IP is selected
as the reference clock.
clock-names:
enum:
- ccm
- ext
required:
- compatible
- reg
allOf:
- $ref: /schemas/pci/pci-device.yaml
unevaluatedProperties: false
examples:
- |
pcie {
#address-cells = <3>;
#size-cells = <2>;
ptp-timer@18,0 {
compatible = "pci1131,ee02";
reg = <0x00c000 0 0 0 0>;
clocks = <&scmi_clk 18>;
clock-names = "ccm";
};
};

View File

@ -251,6 +251,15 @@ patternProperties:
type: object
ecap@[a-f0-9]+$:
description:
PRU-ICSS has a Enhanced Capture (eCAP) event module which can generate
and capture periodic timer based events which will be used for features
like RX Pacing to rise interrupt when the timer event has occurred.
Each PRU-ICSS instance has one eCAP module irrespective of SOCs.
$ref: /schemas/net/ti,pruss-ecap.yaml#
type: object
mii-rt@[a-f0-9]+$:
description: |
Real-Time Ethernet to support multiple industrial communication protocols.

View File

@ -179,7 +179,23 @@ Phase offset measurement and adjustment
Device may provide ability to measure a phase difference between signals
on a pin and its parent dpll device. If pin-dpll phase offset measurement
is supported, it shall be provided with ``DPLL_A_PIN_PHASE_OFFSET``
attribute for each parent dpll device.
attribute for each parent dpll device. The reported phase offset may be
computed as the average of prior values and the current measurement, using
the following formula:
.. math::
curr\_avg = prev\_avg * \frac{2^N-1}{2^N} + new\_val * \frac{1}{2^N}
where `curr_avg` is the current reported phase offset, `prev_avg` is the
previously reported value, `new_val` is the current measurement, and `N` is
the averaging factor. Configured averaging factor value is provided with
``DPLL_A_PHASE_OFFSET_AVG_FACTOR`` attribute of a device and value change can
be requested with the same attribute with ``DPLL_CMD_DEVICE_SET`` command.
================================== ======================================
``DPLL_A_PHASE_OFFSET_AVG_FACTOR`` attr configured value of phase offset
averaging factor
================================== ======================================
Device may also provide ability to adjust a signal phase on a pin.
If pin phase adjustment is supported, minimal and maximal values that pin

View File

@ -154,7 +154,7 @@ properties:
Optional format indicator that is intended only for choosing
the right formatting mechanism when displaying values of this
type.
enum: [ hex, mac, fddi, ipv4, ipv6, uuid ]
enum: [ hex, mac, fddi, ipv4, ipv6, ipv4-or-v6, uuid ]
struct:
description: Name of the nested struct type.
type: string

View File

@ -4,7 +4,7 @@ name: conntrack
protocol: netlink-raw
protonum: 12
doc:
doc: >-
Netfilter connection tracking subsystem over nfnetlink
definitions:

View File

@ -853,6 +853,10 @@ attribute-sets:
type: nest
multi-attr: true
nested-attributes: dl-rate-tc-bws
-
name: health-reporter-burst-period
type: u64
doc: Time (in msec) for recoveries before starting the grace period.
-
name: dl-dev-stats
subset-of: devlink
@ -1216,6 +1220,8 @@ attribute-sets:
name: health-reporter-dump-ts-ns
-
name: health-reporter-auto-dump
-
name: health-reporter-burst-period
-
name: dl-attr-stats
@ -1961,6 +1967,7 @@ operations:
- health-reporter-graceful-period
- health-reporter-auto-recover
- health-reporter-auto-dump
- health-reporter-burst-period
-
name: health-reporter-recover

View File

@ -315,6 +315,10 @@ attribute-sets:
If enabled, dpll device shall monitor and notify all currently
available inputs for changes of their phase offset against the
dpll device.
-
name: phase-offset-avg-factor
type: u32
doc: Averaging factor applied to calculation of reported phase offset.
-
name: pin
enum-name: dpll_a_pin
@ -523,6 +527,7 @@ operations:
- clock-id
- type
- phase-offset-monitor
- phase-offset-avg-factor
dump:
reply: *dev-attrs
@ -540,6 +545,7 @@ operations:
attributes:
- id
- phase-offset-monitor
- phase-offset-avg-factor
-
name: device-create-ntf
doc: Notification about device appearing

View File

@ -204,6 +204,9 @@ definitions:
doc: dst port in case of TCP/UDP/SCTP
-
name: gtp-teid
-
name: ip6-fl
doc: IPv6 Flow Label
-
name: discard
value: 31
@ -1216,6 +1219,30 @@ attribute-sets:
name: udp-ports
type: nest
nested-attributes: tunnel-udp
-
name: fec-hist
attr-cnt-name: --ethtool-a-fec-hist-cnt
attributes:
-
name: pad
type: pad
-
name: bin-low
type: u32
doc: Low bound of FEC bin (inclusive)
-
name: bin-high
type: u32
doc: High bound of FEC bin (inclusive)
-
name: bin-val
type: uint
doc: Error count in the bin (optional if per-lane values exist)
-
name: bin-val-per-lane
type: binary
sub-type: u64
doc: An array of per-lane error counters in the bin (optional)
-
name: fec-stat
attr-cnt-name: __ethtool-a-fec-stat-cnt
@ -1239,6 +1266,11 @@ attribute-sets:
name: corr-bits
type: binary
sub-type: u64
-
name: hist
type: nest
multi-attr: True
nested-attributes: fec-hist
-
name: fec
attr-cnt-name: __ethtool-a-fec-cnt

View File

@ -52,7 +52,7 @@ attribute-sets:
name: local-v6
type: binary
checks:
min-len: 16
exact-len: 16
-
name: peer-v4
type: u32
@ -60,7 +60,7 @@ attribute-sets:
name: peer-v6
type: binary
checks:
min-len: 16
exact-len: 16
-
name: peer-port
type: u16

View File

@ -0,0 +1,13 @@
.. SPDX-License-Identifier: GPL-2.0
.. _specs:
=============================
Netlink Family Specifications
=============================
.. toctree::
:maxdepth: 1
:glob:
*

View File

@ -28,13 +28,13 @@ definitions:
traffic-patterns it can take a long time until the
MPTCP_EVENT_ESTABLISHED is sent.
Attributes: token, family, saddr4 | saddr6, daddr4 | daddr6, sport,
dport, server-side, [flags].
dport, [server-side], [flags].
-
name: established
doc: >-
A MPTCP connection is established (can start new subflows).
Attributes: token, family, saddr4 | saddr6, daddr4 | daddr6, sport,
dport, server-side, [flags].
dport, [server-side], [flags].
-
name: closed
doc: >-
@ -266,6 +266,7 @@ attribute-sets:
-
name: server-side
type: u8
doc: "Deprecated: use 'flags'"
operations:
list:

View File

@ -2,7 +2,7 @@
---
name: netdev
doc:
doc: >-
netdev configuration over generic netlink.
definitions:
@ -13,33 +13,33 @@ definitions:
entries:
-
name: basic
doc:
doc: >-
XDP features set supported by all drivers
(XDP_ABORTED, XDP_DROP, XDP_PASS, XDP_TX)
-
name: redirect
doc:
doc: >-
The netdev supports XDP_REDIRECT
-
name: ndo-xmit
doc:
doc: >-
This feature informs if netdev implements ndo_xdp_xmit callback.
-
name: xsk-zerocopy
doc:
doc: >-
This feature informs if netdev supports AF_XDP in zero copy mode.
-
name: hw-offload
doc:
doc: >-
This feature informs if netdev supports XDP hw offloading.
-
name: rx-sg
doc:
doc: >-
This feature informs if netdev implements non-linear XDP buffer
support in the driver napi callback.
-
name: ndo-xmit-sg
doc:
doc: >-
This feature informs if netdev implements non-linear XDP buffer
support in ndo_xdp_xmit callback.
-
@ -67,15 +67,15 @@ definitions:
entries:
-
name: tx-timestamp
doc:
doc: >-
HW timestamping egress packets is supported by the driver.
-
name: tx-checksum
doc:
doc: >-
L3 checksum HW offload is supported by the driver.
-
name: tx-launch-time-fifo
doc:
doc: >-
Launch time HW offload is supported by the driver.
-
name: queue-type

View File

@ -4,7 +4,7 @@ name: nftables
protocol: netlink-raw
protonum: 12
doc:
doc: >-
Netfilter nftables configuration over netlink.
definitions:

View File

@ -3,7 +3,7 @@
name: nl80211
protocol: genetlink-legacy
doc:
doc: >-
Netlink API for 802.11 wireless devices
definitions:

View File

@ -5,7 +5,7 @@ version: 2
protocol: genetlink-legacy
uapi-header: linux/openvswitch.h
doc:
doc: >-
OVS datapath configuration over generic netlink.
definitions:

View File

@ -5,7 +5,7 @@ version: 1
protocol: genetlink-legacy
uapi-header: linux/openvswitch.h
doc:
doc: >-
OVS flow configuration over generic netlink.
definitions:

View File

@ -5,7 +5,7 @@ version: 2
protocol: genetlink-legacy
uapi-header: linux/openvswitch.h
doc:
doc: >-
OVS vport configuration over generic netlink.
definitions:

View File

@ -0,0 +1,187 @@
# SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause)
---
name: psp
doc:
PSP Security Protocol Generic Netlink family.
definitions:
-
type: enum
name: version
entries: [hdr0-aes-gcm-128, hdr0-aes-gcm-256,
hdr0-aes-gmac-128, hdr0-aes-gmac-256]
attribute-sets:
-
name: dev
attributes:
-
name: id
doc: PSP device ID.
type: u32
checks:
min: 1
-
name: ifindex
doc: ifindex of the main netdevice linked to the PSP device.
type: u32
-
name: psp-versions-cap
doc: Bitmask of PSP versions supported by the device.
type: u32
enum: version
enum-as-flags: true
-
name: psp-versions-ena
doc: Bitmask of currently enabled (accepted on Rx) PSP versions.
type: u32
enum: version
enum-as-flags: true
-
name: assoc
attributes:
-
name: dev-id
doc: PSP device ID.
type: u32
checks:
min: 1
-
name: version
doc: |
PSP versions (AEAD and protocol version) used by this association,
dictates the size of the key.
type: u32
enum: version
-
name: rx-key
type: nest
nested-attributes: keys
-
name: tx-key
type: nest
nested-attributes: keys
-
name: sock-fd
doc: Sockets which should be bound to the association immediately.
type: u32
-
name: keys
attributes:
-
name: key
type: binary
-
name: spi
doc: Security Parameters Index (SPI) of the association.
type: u32
operations:
list:
-
name: dev-get
doc: Get / dump information about PSP capable devices on the system.
attribute-set: dev
do:
request:
attributes:
- id
reply: &dev-all
attributes:
- id
- ifindex
- psp-versions-cap
- psp-versions-ena
pre: psp-device-get-locked
post: psp-device-unlock
dump:
reply: *dev-all
-
name: dev-add-ntf
doc: Notification about device appearing.
notify: dev-get
mcgrp: mgmt
-
name: dev-del-ntf
doc: Notification about device disappearing.
notify: dev-get
mcgrp: mgmt
-
name: dev-set
doc: Set the configuration of a PSP device.
attribute-set: dev
do:
request:
attributes:
- id
- psp-versions-ena
reply:
attributes: []
pre: psp-device-get-locked
post: psp-device-unlock
-
name: dev-change-ntf
doc: Notification about device configuration being changed.
notify: dev-get
mcgrp: mgmt
-
name: key-rotate
doc: Rotate the device key.
attribute-set: dev
do:
request:
attributes:
- id
reply:
attributes:
- id
pre: psp-device-get-locked
post: psp-device-unlock
-
name: key-rotate-ntf
doc: Notification about device key getting rotated.
notify: key-rotate
mcgrp: use
-
name: rx-assoc
doc: Allocate a new Rx key + SPI pair, associate it with a socket.
attribute-set: assoc
do:
request:
attributes:
- dev-id
- version
- sock-fd
reply:
attributes:
- dev-id
- rx-key
pre: psp-assoc-device-get-locked
post: psp-device-unlock
-
name: tx-assoc
doc: Add a PSP Tx association.
attribute-set: assoc
do:
request:
attributes:
- dev-id
- version
- tx-key
- sock-fd
reply:
attributes: []
pre: psp-assoc-device-get-locked
post: psp-device-unlock
mcast-groups:
list:
-
name: mgmt
-
name: use
...

View File

@ -5,7 +5,7 @@ protocol: netlink-raw
uapi-header: linux/rtnetlink.h
protonum: 0
doc:
doc: >-
Address configuration over rtnetlink.
definitions:

View File

@ -5,7 +5,7 @@ protocol: netlink-raw
uapi-header: linux/rtnetlink.h
protonum: 0
doc:
doc: >-
Link configuration over rtnetlink.
definitions:
@ -1057,6 +1057,12 @@ attribute-sets:
-
name: netns-immutable
type: u8
-
name: headroom
type: u16
-
name: tailroom
type: u16
-
name: prop-list-link-attrs
subset-of: link-attrs

View File

@ -5,7 +5,7 @@ protocol: netlink-raw
uapi-header: linux/rtnetlink.h
protonum: 0
doc:
doc: >-
IP neighbour management over rtnetlink.
definitions:

View File

@ -5,7 +5,7 @@ protocol: netlink-raw
uapi-header: linux/rtnetlink.h
protonum: 0
doc:
doc: >-
Route configuration over rtnetlink.
definitions:

View File

@ -5,7 +5,7 @@ protocol: netlink-raw
uapi-header: linux/fib_rules.h
protonum: 0
doc:
doc: >-
FIB rule management over rtnetlink.
definitions:

View File

@ -5,7 +5,7 @@ protocol: netlink-raw
uapi-header: linux/pkt_cls.h
protonum: 0
doc:
doc: >-
Netlink raw family for tc qdisc, chain, class and filter configuration
over rtnetlink.

View File

@ -25,8 +25,9 @@ definitions:
attribute-sets:
-
name: team
doc:
The team nested layout of get/set msg looks like
doc: |
The team nested layout of get/set msg looks like::
[TEAM_ATTR_LIST_OPTION]
[TEAM_ATTR_ITEM_OPTION]
[TEAM_ATTR_OPTION_*], ...
@ -39,6 +40,7 @@ attribute-sets:
[TEAM_ATTR_ITEM_PORT]
[TEAM_ATTR_PORT_*], ...
...
name-prefix: team-attr-
attributes:
-

View File

@ -193,6 +193,15 @@ ad_actor_sys_prio
This parameter has effect only in 802.3ad mode and is available through
SysFs interface.
actor_port_prio
In an AD system, this specifies the port priority. The allowed range
is 1 - 65535. If the value is not specified, it takes 255 as the
default value.
This parameter has effect only in 802.3ad mode and is available through
netlink interface.
ad_actor_system
In an AD system, this specifies the mac-address for the actor in
@ -241,10 +250,18 @@ ad_select
ports (slaves). Reselection occurs as described under the
"bandwidth" setting, above.
The bandwidth and count selection policies permit failover of
802.3ad aggregations when partial failure of the active aggregator
occurs. This keeps the aggregator with the highest availability
(either in bandwidth or in number of ports) active at all times.
actor_port_prio or 3
The active aggregator is chosen by the highest total sum of
actor port priorities across its active ports. Note this
priority is actor_port_prio, not per port prio, which is
used for primary reselect.
The bandwidth, count and actor_port_prio selection policies permit
failover of 802.3ad aggregations when partial failure of the active
aggregator occurs. This keeps the aggregator with the highest
availability (either in bandwidth, number of ports, or total value
of port priorities) active at all times.
This option was added in bonding version 3.4.0.
@ -582,10 +599,8 @@ miimon
This determines how often the link state of each slave is
inspected for link failures. A value of zero disables MII
link monitoring. A value of 100 is a good starting point.
The use_carrier option, below, affects how the link state is
determined. See the High Availability section for additional
information. The default value is 100 if arp_interval is not
set.
The default value is 100 if arp_interval is not set.
min_links
@ -896,25 +911,14 @@ updelay
use_carrier
Specifies whether or not miimon should use MII or ETHTOOL
ioctls vs. netif_carrier_ok() to determine the link
status. The MII or ETHTOOL ioctls are less efficient and
utilize a deprecated calling sequence within the kernel. The
netif_carrier_ok() relies on the device driver to maintain its
state with netif_carrier_on/off; at this writing, most, but
not all, device drivers support this facility.
Obsolete option that previously selected between MII /
ETHTOOL ioctls and netif_carrier_ok() to determine link
state.
If bonding insists that the link is up when it should not be,
it may be that your network device driver does not support
netif_carrier_on/off. The default state for netif_carrier is
"carrier on," so if a driver does not support netif_carrier,
it will appear as if the link is always up. In this case,
setting use_carrier to 0 will cause bonding to revert to the
MII / ETHTOOL ioctl method to determine the link state.
All link state checks are now done with netif_carrier_ok().
A value of 1 enables the use of netif_carrier_ok(), a value of
0 will use the deprecated MII / ETHTOOL ioctls. The default
value is 1.
For backwards compatibility, this option's value may be inspected
or set. The only valid setting is 1.
xmit_hash_policy
@ -2036,22 +2040,8 @@ depending upon the device driver to maintain its carrier state, by
querying the device's MII registers, or by making an ethtool query to
the device.
If the use_carrier module parameter is 1 (the default value),
then the MII monitor will rely on the driver for carrier state
information (via the netif_carrier subsystem). As explained in the
use_carrier parameter information, above, if the MII monitor fails to
detect carrier loss on the device (e.g., when the cable is physically
disconnected), it may be that the driver does not support
netif_carrier.
If use_carrier is 0, then the MII monitor will first query the
device's (via ioctl) MII registers and check the link state. If that
request fails (not just that it returns carrier down), then the MII
monitor will make an ethtool ETHTOOL_GLINK request to attempt to obtain
the same information. If both methods fail (i.e., the driver either
does not support or had some error in processing both the MII register
and ethtool requests), then the MII monitor will assume the link is
up.
The MII monitor relies on the driver for carrier state information (via
the netif_carrier subsystem).
8. Potential Sources of Trouble
===============================
@ -2135,34 +2125,6 @@ This will load tg3 and e1000 modules before loading the bonding one.
Full documentation on this can be found in the modprobe.d and modprobe
manual pages.
8.3. Painfully Slow Or No Failed Link Detection By Miimon
---------------------------------------------------------
By default, bonding enables the use_carrier option, which
instructs bonding to trust the driver to maintain carrier state.
As discussed in the options section, above, some drivers do
not support the netif_carrier_on/_off link state tracking system.
With use_carrier enabled, bonding will always see these links as up,
regardless of their actual state.
Additionally, other drivers do support netif_carrier, but do
not maintain it in real time, e.g., only polling the link state at
some fixed interval. In this case, miimon will detect failures, but
only after some long period of time has expired. If it appears that
miimon is very slow in detecting link failures, try specifying
use_carrier=0 to see if that improves the failure detection time. If
it does, then it may be that the driver checks the carrier state at a
fixed interval, but does not cache the MII register values (so the
use_carrier=0 method of querying the registers directly works). If
use_carrier=0 does not improve the failover, then the driver may cache
the registers, or the problem may be elsewhere.
Also, remember that miimon only checks for the device's
carrier state. It has no way to determine the state of devices on or
beyond other ports of a switch, or if a switch is refusing to pass
traffic while still maintaining carrier on.
9. SNMP agents
===============

View File

@ -50,6 +50,7 @@ Contents:
neterion/s2io
netronome/nfp
pensando/ionic
qualcomm/ppe/ppe
smsc/smc9
stmicro/stmmac
ti/cpsw

View File

@ -1348,7 +1348,7 @@ Device Counters
is in a congested state.
If pci_bw_inbound_high == pci_bw_inbound_low then the device is not congested.
If pci_bw_inbound_high > pci_bw_inbound_low then the device is congested.
- Tnformative
- Informative
* - `pci_bw_inbound_low`
- The number of times the device crossed the low inbound PCIe bandwidth
@ -1373,3 +1373,8 @@ Device Counters
If pci_bw_outbound_high == pci_bw_outbound_low then the device is not congested.
If pci_bw_outbound_high > pci_bw_outbound_low then the device is congested.
- Informative
* - `pci_bw_stale_event`
- The number of times the device fired a PCIe congestion event but on query
there was no change in state.
- Informative

View File

@ -69,6 +69,25 @@ On host boot the latest UEFI driver is always used, no explicit activation
is required. Firmware activation is required to run new control firmware. cmrt
firmware can only be activated by power cycling the NIC.
Health reporters
----------------
fw reporter
~~~~~~~~~~~
The ``fw`` health reporter tracks FW crashes. Dumping the reporter will
show the core dump of the most recent FW crash, and if no FW crash has
happened since power cycle - a snapshot of the FW memory. Diagnose callback
shows FW uptime based on the most recently received heartbeat message
(the crashes are detected by checking if uptime goes down).
otp reporter
~~~~~~~~~~~~
OTP memory ("fuses") are used for secure boot and anti-rollback
protection. The OTP memory is ECC protected, ECC errors indicate
either manufacturing defect or part deteriorating with age.
Statistics
----------
@ -160,3 +179,14 @@ behavior and potential performance bottlenecks.
credit exhaustion
- ``pcie_ob_rd_no_np_cred``: Read requests dropped due to non-posted
credit exhaustion
XDP Length Error:
~~~~~~~~~~~~~~~~~
For XDP programs without frags support, fbnic tries to make sure that MTU fits
into a single buffer. If an oversized frame is received and gets fragmented,
it is dropped and the following netlink counters are updated
- ``rx-length``: number of frames dropped due to lack of fragmentation
support in the attached XDP program
- ``rx-errors``: total number of packets with errors received on the interface

View File

@ -0,0 +1,194 @@
.. SPDX-License-Identifier: GPL-2.0
===============================================
PPE Ethernet Driver for Qualcomm IPQ SoC Family
===============================================
Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
Author: Lei Wei <quic_leiwei@quicinc.com>
Contents
========
- `PPE Overview`_
- `PPE Driver Overview`_
- `PPE Driver Supported SoCs`_
- `Enabling the Driver`_
- `Debugging`_
PPE Overview
============
IPQ (Qualcomm Internet Processor) SoC (System-on-Chip) series is Qualcomm's series of
networking SoC for Wi-Fi access points. The PPE (Packet Process Engine) is the Ethernet
packet process engine in the IPQ SoC.
Below is a simplified hardware diagram of IPQ9574 SoC which includes the PPE engine and
other blocks which are in the SoC but outside the PPE engine. These blocks work together
to enable the Ethernet for the IPQ SoC::
+------+ +------+ +------+ +------+ +------+ +------+ start +-------+
|netdev| |netdev| |netdev| |netdev| |netdev| |netdev|<------|PHYLINK|
+------+ +------+ +------+ +------+ +------+ +------+ stop +-+-+-+-+
| | | ^
+-------+ +-------------------------+--------+----------------------+ | | |
| GCC | | | EDMA | | | | |
+---+---+ | PPE +---+----+ | | | |
| clk | | | | | |
+-------->| +-----------------------+------+-----+---------------+ | | | |
| | Switch Core |Port0 | |Port7(EIP FIFO)| | | | |
| | +---+--+ +------+--------+ | | | |
| | | | | | | | |
+-------+ | | +------+---------------+----+ | | | | |
|CMN PLL| | | +---+ +---+ +----+ | +--------+ | | | | | |
+---+---+ | | |BM | |QM | |SCH | | | L2/L3 | ....... | | | | | |
| | | | +---+ +---+ +----+ | +--------+ | | | | | |
| | | | +------+--------------------+ | | | | |
| | | | | | | | | |
| v | | +-----+-+-----+-+-----+-+-+---+--+-----+-+-----+ | | | | |
| +------+ | | |Port1| |Port2| |Port3| |Port4| |Port5| |Port6| | | | | |
| |NSSCC | | | +-----+ +-----+ +-----+ +-----+ +-----+ +-----+ | | mac| | |
| +-+-+--+ | | |MAC0 | |MAC1 | |MAC2 | |MAC3 | |MAC4 | |MAC5 | | |<---+ | |
| ^ | |clk | | +-----+-+-----+-+-----+-+-----+--+-----+-+-----+ | | ops | |
| | | +------>| +----|------|-------|-------|---------|--------|-----+ | | |
| | | +---------------------------------------------------------+ | |
| | | | | | | | | | |
| | | MII clk | QSGMII USXGMII USXGMII | |
| | +--------------->| | | | | | | |
| | +-------------------------+ +---------+ +---------+ | |
| |125/312.5MHz clk| (PCS0) | | (PCS1) | | (PCS2) | pcs ops | |
| +----------------+ UNIPHY0 | | UNIPHY1 | | UNIPHY2 |<--------+ |
+----------------->| | | | | | |
| 31.25MHz ref clk +-------------------------+ +---------+ +---------+ |
| | | | | | | |
| +-----------------------------------------------------+ |
|25/50MHz ref clk| +-------------------------+ +------+ +------+ | link |
+--------------->| | QUAD PHY | | PHY4 | | PHY5 | |---------+
| +-------------------------+ +------+ +------+ | change
| |
| MDIO bus |
+-----------------------------------------------------+
The CMN (Common) PLL, NSSCC (Networking Sub System Clock Controller) and GCC (Global
Clock Controller) blocks are in the SoC and act as clock providers.
The UNIPHY block is in the SoC and provides the PCS (Physical Coding Sublayer) and
XPCS (10-Gigabit Physical Coding Sublayer) functions to support different interface
modes between the PPE MAC and the external PHY.
This documentation focuses on the descriptions of PPE engine and the PPE driver.
The Ethernet functionality in the PPE (Packet Process Engine) is comprised of three
components: the switch core, port wrapper and Ethernet DMA.
The Switch core in the IPQ9574 PPE has maximum of 6 front panel ports and two FIFO
interfaces. One of the two FIFO interfaces is used for Ethernet port to host CPU
communication using Ethernet DMA. The other one is used to communicate to the EIP
engine which is used for IPsec offload. On the IPQ9574, the PPE includes 6 GMAC/XGMACs
that can be connected with external Ethernet PHY. Switch core also includes BM (Buffer
Management), QM (Queue Management) and SCH (Scheduler) modules for supporting the
packet processing.
The port wrapper provides connections from the 6 GMAC/XGMACS to UNIPHY (PCS) supporting
various modes such as SGMII/QSGMII/PSGMII/USXGMII/10G-BASER. There are 3 UNIPHY (PCS)
instances supported on the IPQ9574.
Ethernet DMA is used to transmit and receive packets between the Ethernet subsystem
and ARM host CPU.
The following lists the main blocks in the PPE engine which will be driven by this
PPE driver:
- BM
BM is the hardware buffer manager for the PPE switch ports.
- QM
Queue Manager for managing the egress hardware queues of the PPE switch ports.
- SCH
The scheduler which manages the hardware traffic scheduling for the PPE switch ports.
- L2
The L2 block performs the packet bridging in the switch core. The bridge domain is
represented by the VSI (Virtual Switch Instance) domain in PPE. FDB learning can be
enabled based on the VSI domain and bridge forwarding occurs within the VSI domain.
- MAC
The PPE in the IPQ9574 supports up to six MACs (MAC0 to MAC5) which are corresponding
to six switch ports (port1 to port6). The MAC block is connected with external PHY
through the UNIPHY PCS block. Each MAC block includes the GMAC and XGMAC blocks and
the switch port can select to use GMAC or XMAC through a MUX selection according to
the external PHY's capability.
- EDMA (Ethernet DMA)
The Ethernet DMA is used to transmit and receive Ethernet packets between the PPE
ports and the ARM cores.
The received packet on a PPE MAC port can be forwarded to another PPE MAC port. It can
be also forwarded to internal switch port0 so that the packet can be delivered to the
ARM cores using the Ethernet DMA (EDMA) engine. The Ethernet DMA driver will deliver the
packet to the corresponding 'netdevice' interface.
The software instantiations of the PPE MAC (netdevice), PCS and external PHYs interact
with the Linux PHYLINK framework to manage the connectivity between the PPE ports and
the connected PHYs, and the port link states. This is also illustrated in above diagram.
PPE Driver Overview
===================
PPE driver is Ethernet driver for the Qualcomm IPQ SoC. It is a single platform driver
which includes the PPE part and Ethernet DMA part. The PPE part initializes and drives the
various blocks in PPE switch core such as BM/QM/L2 blocks and the PPE MACs. The EDMA part
drives the Ethernet DMA for packet transfer between PPE ports and ARM cores, and enables
the netdevice driver for the PPE ports.
The PPE driver files in drivers/net/ethernet/qualcomm/ppe/ are listed as below:
- Makefile
- ppe.c
- ppe.h
- ppe_config.c
- ppe_config.h
- ppe_debugfs.c
- ppe_debugfs.h
- ppe_regs.h
The ppe.c file contains the main PPE platform driver and undertakes the initialization of
PPE switch core blocks such as QM, BM and L2. The configuration APIs for these hardware
blocks are provided in the ppe_config.c file.
The ppe.h defines the PPE device data structure which will be used by PPE driver functions.
The ppe_debugfs.c enables the PPE statistics counters such as PPE port Rx and Tx counters,
CPU code counters and queue counters.
PPE Driver Supported SoCs
=========================
The PPE driver supports the following IPQ SoC:
- IPQ9574
Enabling the Driver
===================
The driver is located in the menu structure at::
-> Device Drivers
-> Network device support (NETDEVICES [=y])
-> Ethernet driver support
-> Qualcomm devices
-> Qualcomm Technologies, Inc. PPE Ethernet support
If the driver is built as a module, the module will be called qcom-ppe.
The PPE driver functionally depends on the CMN PLL and NSSCC clock controller drivers.
Please make sure the dependent modules are installed before installing the PPE driver
module.
Debugging
=========
The PPE hardware counters can be accessed using debugfs interface from the
``/sys/kernel/debug/ppe/`` directory.

View File

@ -50,7 +50,7 @@ Once an error is reported, devlink health will perform the following actions:
* Auto recovery attempt is being done. Depends on:
- Auto-recovery configuration
- Grace period vs. time passed since last recover
- Grace period (and burst period) vs. time passed since last recover
Devlink formatted message
=========================

View File

@ -143,3 +143,11 @@ own name.
* - ``clock_id``
- u64
- Clock ID used by the device for registering DPLL devices and pins.
* - ``total_vfs``
- u32
- The max number of Virtual Functions (VFs) exposed by the PF.
after reboot/pci reset, 'sriov_totalvfs' entry under the device's sysfs
directory will report this value.
* - ``num_doorbells``
- u32
- Controls the number of doorbells used by the device.

View File

@ -56,18 +56,18 @@ general.
:maxdepth: 1
devlink-dpipe
devlink-eswitch-attr
devlink-flash
devlink-health
devlink-info
devlink-flash
devlink-linecard
devlink-params
devlink-port
devlink-region
devlink-resource
devlink-reload
devlink-resource
devlink-selftests
devlink-trap
devlink-linecard
devlink-eswitch-attr
Driver-specific documentation
-----------------------------
@ -78,12 +78,14 @@ parameters, info versions, and other features it supports.
.. toctree::
:maxdepth: 1
am65-nuss-cpsw-switch
bnxt
etas_es58x
hns3
i40e
ionic
ice
ionic
iosm
ixgbe
kvaser_pciefd
kvaser_usb
@ -93,11 +95,9 @@ parameters, info versions, and other features it supports.
mv88e6xxx
netdevsim
nfp
qed
ti-cpsw-switch
am65-nuss-cpsw-switch
prestera
iosm
octeontx2
prestera
qed
sfc
ti-cpsw-switch
zl3073x

View File

@ -15,23 +15,62 @@ Parameters
* - Name
- Mode
- Validation
- Notes
* - ``enable_roce``
- driverinit
- Type: Boolean
If the device supports RoCE disablement, RoCE enablement state controls
- Boolean
- If the device supports RoCE disablement, RoCE enablement state controls
device support for RoCE capability. Otherwise, the control occurs in the
driver stack. When RoCE is disabled at the driver level, only raw
ethernet QPs are supported.
* - ``io_eq_size``
- driverinit
- The range is between 64 and 4096.
-
* - ``event_eq_size``
- driverinit
- The range is between 64 and 4096.
-
* - ``max_macs``
- driverinit
- The range is between 1 and 2^31. Only power of 2 values are supported.
-
* - ``enable_sriov``
- permanent
- Boolean
- Applies to each physical function (PF) independently, if the device
supports it. Otherwise, it applies symmetrically to all PFs.
* - ``total_vfs``
- permanent
- The range is between 1 and a device-specific max.
- Applies to each physical function (PF) independently, if the device
supports it. Otherwise, it applies symmetrically to all PFs.
Note: permanent parameters such as ``enable_sriov`` and ``total_vfs`` require FW reset to take effect
.. code-block:: bash
# setup parameters
devlink dev param set pci/0000:01:00.0 name enable_sriov value true cmode permanent
devlink dev param set pci/0000:01:00.0 name total_vfs value 8 cmode permanent
# Fw reset
devlink dev reload pci/0000:01:00.0 action fw_activate
# for PCI related config such as sriov PCI reset/rescan is required:
echo 1 >/sys/bus/pci/devices/0000:01:00.0/remove
echo 1 >/sys/bus/pci/rescan
grep ^ /sys/bus/pci/devices/0000:01:00.0/sriov_*
* - ``num_doorbells``
- driverinit
- This controls the number of channel doorbells used by the netdev. In all
cases, an additional doorbell is allocated and used for non-channel
communication (e.g. for PTP, HWS, etc.). Supported values are:
- 0: No channel-specific doorbells, use the global one for everything.
- [1, max_num_channels]: Spread netdev channels equally across these
doorbells.
The ``mlx5`` driver also implements the following driver-specific
parameters.
@ -116,6 +155,68 @@ parameters.
- u32
- driverinit
- Control the size (in packets) of the hairpin queues.
* - ``pcie_cong_inbound_high``
- u16
- driverinit
- High threshold configuration for PCIe congestion events. The firmware
will send an event once device side inbound PCIe traffic went
above the configured high threshold for a long enough period (at least
200ms).
See pci_bw_inbound_high ethtool stat.
Units are 0.01 %. Accepted values are in range [0, 10000].
pcie_cong_inbound_low < pcie_cong_inbound_high.
Default value: 9000 (Corresponds to 90%).
* - ``pcie_cong_inbound_low``
- u16
- driverinit
- Low threshold configuration for PCIe congestion events. The firmware
will send an event once device side inbound PCIe traffic went
below the configured low threshold, only after having been previously in
a congested state.
See pci_bw_inbound_low ethtool stat.
Units are 0.01 %. Accepted values are in range [0, 10000].
pcie_cong_inbound_low < pcie_cong_inbound_high.
Default value: 7500.
* - ``pcie_cong_outbound_high``
- u16
- driverinit
- High threshold configuration for PCIe congestion events. The firmware
will send an event once device side outbound PCIe traffic went
above the configured high threshold for a long enough period (at least
200ms).
See pci_bw_outbound_high ethtool stat.
Units are 0.01 %. Accepted values are in range [0, 10000].
pcie_cong_outbound_low < pcie_cong_outbound_high.
Default value: 9000 (Corresponds to 90%).
* - ``pcie_cong_outbound_low``
- u16
- driverinit
- Low threshold configuration for PCIe congestion events. The firmware
will send an event once device side outbound PCIe traffic went
below the configured low threshold, only after having been previously in
a congested state.
See pci_bw_outbound_low ethtool stat.
Units are 0.01 %. Accepted values are in range [0, 10000].
pcie_cong_outbound_low < pcie_cong_outbound_high.
Default value: 7500.
* - ``cqe_compress_type``
- string
- permanent
- Configure which mechanism/algorithm should be used by the NIC that will
affect the rate (aggressiveness) of compressed CQEs depending on PCIe bus
conditions and other internal NIC factors. This mode affects all queues
that enable compression.
* ``balanced`` : Merges fewer CQEs, resulting in a moderate compression ratio but maintaining a balance between bandwidth savings and performance
* ``aggressive`` : Merges more CQEs into a single entry, achieving a higher compression rate and maximizing performance, particularly under high traffic loads
The ``mlx5`` driver supports reloading via ``DEVLINK_CMD_RELOAD``
@ -284,6 +385,12 @@ Description of the vnic counters:
amount of Interconnect Host Memory (ICM) consumed by the vnic in
granularity of 4KB. ICM is host memory allocated by SW upon HCA request
and is used for storing data structures that control HCA operation.
- bar_uar_access
number of WRITE or READ access operations to the UAR on the PCIe BAR.
- odp_local_triggered_page_fault
number of locally-triggered page-faults due to ODP.
- odp_remote_triggered_page_fault
number of remotly-triggered page-faults due to ODP.
User commands examples:

View File

@ -49,3 +49,17 @@ The ``zl3073x`` driver reports the following versions
- running
- 1.3.0.1
- Device configuration version customized by OEM
Flash Update
============
The ``zl3073x`` driver implements support for flash update using the
``devlink-flash`` interface. It supports updating the device flash using a
combined flash image ("bundle") that contains multiple components (firmware
parts and configurations).
During the flash procedure, the standard firmware interface is not available,
so the driver unregisters all DPLLs and associated pins, and re-registers them
once the flash procedure is complete.
The driver does not support any overwrite mask flags.

View File

@ -25,11 +25,11 @@ These routines must be supported by userspace tools dns.upcall, cifs.upcall and
request-key. It is under development and does not yet provide the full feature
set. The features it does support include:
(*) Implements the dns_resolver key_type to contact userspace.
* Implements the dns_resolver key_type to contact userspace.
It does not yet support the following AFS features:
(*) Dns query support for AFSDB resource record.
* DNS query support for AFSDB resource record.
This code is extracted from the CIFS filesystem.
@ -64,44 +64,42 @@ before the more general line given above as the first match is the one taken::
Usage
=====
To make use of this facility, one of the following functions that are
implemented in the module can be called after doing::
To make use of this facility, first ``dns_resolver.h`` must be included::
#include <linux/dns_resolver.h>
::
Then queries may be made by calling::
int dns_query(const char *type, const char *name, size_t namelen,
const char *options, char **_result, time_t *_expiry);
This is the basic access function. It looks for a cached DNS query and if
it doesn't find it, it upcalls to userspace to make a new DNS query, which
may then be cached. The key description is constructed as a string of the
form::
This is the basic access function. It looks for a cached DNS query and if
it doesn't find it, it upcalls to userspace to make a new DNS query, which
may then be cached. The key description is constructed as a string of the
form::
[<type>:]<name>
where <type> optionally specifies the particular upcall program to invoke,
and thus the type of query to do, and <name> specifies the string to be
looked up. The default query type is a straight hostname to IP address
set lookup.
where <type> optionally specifies the particular upcall program to invoke,
and thus the type of query, and <name> specifies the string to be looked up.
The default query type is a straight hostname to IP address set lookup.
The name parameter is not required to be a NUL-terminated string, and its
length should be given by the namelen argument.
The name parameter is not required to be a NUL-terminated string, and its
length should be given by the namelen argument.
The options parameter may be NULL or it may be a set of options
appropriate to the query type.
The options parameter may be NULL or it may be a set of options
appropriate to the query type.
The return value is a string appropriate to the query type. For instance,
for the default query type it is just a list of comma-separated IPv4 and
IPv6 addresses. The caller must free the result.
The return value is a string appropriate to the query type. For instance,
for the default query type it is just a list of comma-separated IPv4 and
IPv6 addresses. The caller must free the result.
The length of the result string is returned on success, and a negative
error code is returned otherwise. -EKEYREJECTED will be returned if the
DNS lookup failed.
The length of the result string is returned on success, and a negative
error code is returned otherwise. -EKEYREJECTED will be returned if the
DNS lookup failed.
If _expiry is non-NULL, the expiry time (TTL) of the result will be
returned also.
If _expiry is non-NULL, the expiry time (TTL) of the result will be
returned also.
The kernel maintains an internal keyring in which it caches looked up keys.
This can be cleared by any process that has the CAP_SYS_ADMIN capability by
@ -142,8 +140,8 @@ the key will be discarded and recreated when the data it holds has expired.
dns_query() returns a copy of the value attached to the key, or an error if
that is indicated instead.
See <file:Documentation/security/keys/request-key.rst> for further
information about request-key function.
See Documentation/security/keys/request-key.rst for further information about
request-key function.
Debugging

View File

@ -1541,6 +1541,11 @@ Drivers fill in the statistics in the following structure:
.. kernel-doc:: include/linux/ethtool.h
:identifiers: ethtool_fec_stats
Statistics may have FEC bins histogram attribute ``ETHTOOL_A_FEC_STAT_HIST``
as defined in IEEE 802.3ck-2022 and 802.3df-2024. Nested attributes will have
the range of FEC errors in the bin (inclusive) and the amount of error events
in the bin.
FEC_SET
=======

View File

@ -57,7 +57,7 @@ Contents:
filter
generic-hdlc
generic_netlink
netlink_spec/index
../netlink/specs/index
gen_stats
gtp
ila
@ -101,6 +101,7 @@ Contents:
ppp_generic
proc_net_tcp
pse-pd/index
psp
radiotap-headers
rds
regulatory

View File

@ -209,7 +209,7 @@ neigh/default/unres_qlen_bytes - INTEGER
Setting negative value is meaningless and will return error.
Default: SK_WMEM_MAX, (same as net.core.wmem_default).
Default: SK_WMEM_DEFAULT, (same as net.core.wmem_default).
Exact value depends on architecture and kernel options,
but should be enough to allow queuing 256 packets
@ -443,23 +443,56 @@ tcp_early_retrans - INTEGER
tcp_ecn - INTEGER
Control use of Explicit Congestion Notification (ECN) by TCP.
ECN is used only when both ends of the TCP connection indicate
support for it. This feature is useful in avoiding losses due
to congestion by allowing supporting routers to signal
congestion before having to drop packets.
ECN is used only when both ends of the TCP connection indicate support
for it. This feature is useful in avoiding losses due to congestion by
allowing supporting routers to signal congestion before having to drop
packets. A host that supports ECN both sends ECN at the IP layer and
feeds back ECN at the TCP layer. The highest variant of ECN feedback
that both peers support is chosen by the ECN negotiation (Accurate ECN,
ECN, or no ECN).
The highest negotiated variant for incoming connection requests
and the highest variant requested by outgoing connection
attempts:
===== ==================== ====================
Value Incoming connections Outgoing connections
===== ==================== ====================
0 No ECN No ECN
1 ECN ECN
2 ECN No ECN
3 AccECN AccECN
4 AccECN ECN
5 AccECN No ECN
===== ==================== ====================
Default: 2
tcp_ecn_option - INTEGER
Control Accurate ECN (AccECN) option sending when AccECN has been
successfully negotiated during handshake. Send logic inhibits
sending AccECN options regarless of this setting when no AccECN
option has been seen for the reverse direction.
Possible values are:
= =====================================================
0 Disable ECN. Neither initiate nor accept ECN.
1 Enable ECN when requested by incoming connections and
also request ECN on outgoing connection attempts.
2 Enable ECN when requested by incoming connections
but do not request ECN on outgoing connections.
= =====================================================
= ============================================================
0 Never send AccECN option. This also disables sending AccECN
option in SYN/ACK during handshake.
1 Send AccECN option sparingly according to the minimum option
rules outlined in draft-ietf-tcpm-accurate-ecn.
2 Send AccECN option on every packet whenever it fits into TCP
option space.
= ============================================================
Default: 2
tcp_ecn_option_beacon - INTEGER
Control Accurate ECN (AccECN) option sending frequency per RTT and it
takes effect only when tcp_ecn_option is set to 2.
Default: 3 (AccECN will be send at least 3 times per RTT)
tcp_ecn_fallback - BOOLEAN
If the kernel detects that ECN connection misbehaves, enable fall
back to non-ECN. Currently, this knob implements the fallback
@ -805,8 +838,8 @@ tcp_rmem - vector of 3 INTEGERs: min, default, max
This value results in initial window of 65535.
max: maximal size of receive buffer allowed for automatically
selected receiver buffers for TCP socket. This value does not override
net.core.rmem_max. Calling setsockopt() with SO_RCVBUF disables
selected receiver buffers for TCP socket.
Calling setsockopt() with SO_RCVBUF disables
automatic tuning of that socket's receive buffer size, in which
case this value is ignored.
Default: between 131072 and 32MB, depending on RAM size.
@ -3508,16 +3541,10 @@ cookie_hmac_alg - STRING
a listening sctp socket to a connecting client in the INIT-ACK chunk.
Valid values are:
* md5
* sha1
* sha256
* none
Ability to assign md5 or sha1 as the selected alg is predicated on the
configuration of those algorithms at build time (CONFIG_CRYPTO_MD5 and
CONFIG_CRYPTO_SHA1).
Default: Dependent on configuration. MD5 if available, else SHA1 if
available, else none.
Default: sha256
rcvbuf_policy - INTEGER
Determines if the receive buffer is attributed to the socket or to

View File

@ -8,9 +8,11 @@ MPTCP Sysfs variables
===============================
add_addr_timeout - INTEGER (seconds)
Set the timeout after which an ADD_ADDR control message will be
resent to an MPTCP peer that has not acknowledged a previous
ADD_ADDR message.
Set the maximum value of timeout after which an ADD_ADDR control message
will be resent to an MPTCP peer that has not acknowledged a previous
ADD_ADDR message. A dynamically estimated retransmission timeout based
on the estimated connection round-trip-time is used if this value is
lower than the maximum one.
Do not retransmit if set to 0.

View File

@ -66,7 +66,7 @@ the same rules are applied for all the connections (see: ``ip mptcp``) ; and the
userspace one (``userspace``), controlled by a userspace daemon (i.e. `mptcpd
<https://mptcpd.mptcp.dev/>`_) where different rules can be applied for each
connection. The path managers can be controlled via a Netlink API; see
netlink_spec/mptcp_pm.rst.
../netlink/specs/mptcp_pm.rst.
To be able to use multiple IP addresses on a host to create multiple *subflows*
(paths), the default in-kernel MPTCP path-manager needs to know which IP

View File

@ -26,8 +26,8 @@ u64 bytes_acked read_w
u32 dsack_dups
u32 snd_una read_mostly read_write tcp_wnd_end,tcp_urg_mode,tcp_minshall_check,tcp_cwnd_validate(tx);tcp_ack,tcp_may_update_window,tcp_clean_rtx_queue(write),tcp_ack_tstamp(rx)
u32 snd_sml read_write tcp_minshall_check,tcp_minshall_update
u32 rcv_tstamp read_mostly tcp_ack
void * tcp_clean_acked read_mostly tcp_ack
u32 rcv_tstamp read_write read_write tcp_ack
void * tcp_clean_acked read_mostly tcp_ack
u32 lsndtime read_write tcp_slow_start_after_idle_check,tcp_event_data_sent
u32 last_oow_ack_time
u32 compressed_ack_rcv_nxt
@ -57,7 +57,7 @@ u8:1 is_sack_reneg read_m
u8:2 fastopen_client_fail
u8:4 nonagle read_write tcp_skb_entail,tcp_push_pending_frames
u8:1 thin_lto
u8:1 recvmsg_inq
u8:1 recvmsg_inq read_mostly tcp_recvmsg
u8:1 repair read_mostly tcp_write_xmit
u8:1 frto
u8 repair_queue
@ -101,6 +101,18 @@ u32 prr_delivered
u32 prr_out read_mostly read_mostly tcp_rate_skb_sent,tcp_newly_delivered(tx);tcp_ack,tcp_rate_gen,tcp_clean_rtx_queue(rx)
u32 delivered read_mostly read_write tcp_rate_skb_sent, tcp_newly_delivered(tx);tcp_ack, tcp_rate_gen, tcp_clean_rtx_queue (rx)
u32 delivered_ce read_mostly read_write tcp_rate_skb_sent(tx);tcp_rate_gen(rx)
u32 received_ce read_mostly read_write
u32[3] received_ecn_bytes read_mostly read_write
u8:4 received_ce_pending read_mostly read_write
u32[3] delivered_ecn_bytes read_write
u8:2 syn_ect_snt write_mostly read_write
u8:2 syn_ect_rcv read_mostly read_write
u8:2 accecn_minlen write_mostly read_write
u8:2 est_ecnfield read_write
u8:2 accecn_opt_demand read_mostly read_write
u8:2 prev_ecnfield read_write
u64 accecn_opt_tstamp read_write
u8:4 accecn_fail_mode
u32 lost read_mostly tcp_ack
u32 app_limited read_write read_mostly tcp_rate_check_app_limited,tcp_rate_skb_sent(tx);tcp_rate_gen(rx)
u64 first_tx_mstamp read_write tcp_rate_skb_sent

View File

@ -1 +0,0 @@
*.rst

View File

@ -1,4 +0,0 @@
SPDX-License-Identifier: GPL-2.0
This file is populated during the build of the documentation (htmldocs) by the
tools/net/ynl/pyynl/ynl_gen_rst.py script.

View File

@ -20,7 +20,7 @@ sometimes quite different) ethernet controllers connected to the same
management bus, it is difficult to ensure safe use of the bus.
Since the PHYs are devices, and the management busses through which they are
accessed are, in fact, busses, the PHY Abstraction Layer treats them as such.
accessed are, in fact, busses, the PHY Abstraction Layer (PAL) treats them as such.
In doing so, it has these goals:
#. Increase code-reuse

View File

@ -0,0 +1,183 @@
.. SPDX-License-Identifier: GPL-2.0-only
=====================
PSP Security Protocol
=====================
Protocol
========
PSP Security Protocol (PSP) was defined at Google and published in:
https://raw.githubusercontent.com/google/psp/main/doc/PSP_Arch_Spec.pdf
This section briefly covers protocol aspects crucial for understanding
the kernel API. Refer to the protocol specification for further details.
Note that the kernel implementation and documentation uses the term
"device key" in place of "master key", it is both less confusing
to an average developer and is less likely to run afoul any naming
guidelines.
Derived Rx keys
---------------
PSP borrows some terms and mechanisms from IPsec. PSP was designed
with HW offloads in mind. The key feature of PSP is that Rx keys for every
connection do not have to be stored by the receiver but can be derived
from device key and information present in packet headers.
This makes it possible to implement receivers which require a constant
amount of memory regardless of the number of connections (``O(1)`` scaling).
Tx keys have to be stored like with any other protocol, but Tx is much
less latency sensitive than Rx, and delays in fetching keys from slow
memory is less likely to cause packet drops. Preferably, the Tx keys
should be provided with the packet (e.g. as part of the descriptors).
Key rotation
------------
The device key known only to the receiver is fundamental to the design.
Per specification this state cannot be directly accessible (it must be
impossible to read it out of the hardware of the receiver NIC).
Moreover, it has to be "rotated" periodically (usually daily). Rotation
means that new device key gets generated (by a random number generator
of the device), and used for all new connections. To avoid disrupting
old connections the old device key remains in the NIC. A phase bit
carried in the packet headers indicates which generation of device key
the packet has been encrypted with.
User facing API
===============
PSP is designed primarily for hardware offloads. There is currently
no software fallback for systems which do not have PSP capable NICs.
There is also no standard (or otherwise defined) way of establishing
a PSP-secured connection or exchanging the symmetric keys.
The expectation is that higher layer protocols will take care of
protocol and key negotiation. For example one may use TLS key exchange,
announce the PSP capability, and switch to PSP if both endpoints
are PSP-capable.
All configuration of PSP is performed via the PSP netlink family.
Device discovery
----------------
The PSP netlink family defines operations to retrieve information
about the PSP devices available on the system, configure them and
access PSP related statistics.
Securing a connection
---------------------
PSP encryption is currently only supported for TCP connections.
Rx and Tx keys are allocated separately. First the ``rx-assoc``
Netlink command needs to be issued, specifying a target TCP socket.
Kernel will allocate a new PSP Rx key from the NIC and associate it
with given socket. At this stage socket will accept both PSP-secured
and plain text TCP packets.
Tx keys are installed using the ``tx-assoc`` Netlink command.
Once the Tx keys are installed, all data read from the socket will
be PSP-secured. In other words act of installing Tx keys has a secondary
effect on the Rx direction.
There is an intermediate period after ``tx-assoc`` successfully
returns and before the TCP socket encounters it's first PSP
authenticated packet, where the TCP stack will allow certain nondata
packets, i.e. ACKs, FINs, and RSTs, to enter TCP receive processing
even if not PSP authenticated. During the ``tx-assoc`` call, the TCP
socket's ``rcv_nxt`` field is recorded. At this point, ACKs and RSTs
will be accepted with any sequence number, while FINs will only be
accepted at the latched value of ``rcv_nxt``. Once the TCP stack
encounters the first TCP packet containing PSP authenticated data, the
other end of the connection must have executed the ``tx-assoc``
command, so any TCP packet, including those without data, will be
dropped before receive processing if it is not successfully
authenticated. This is summarized in the table below. The
aforementioned state of rejecting all non-PSP packets is labeled "PSP
Full".
+----------------+------------+------------+-------------+-------------+
| Event | Normal TCP | Rx PSP | Tx PSP | PSP Full |
+================+============+============+=============+=============+
| Rx plain | accept | accept | drop | drop |
| (data) | | | | |
+----------------+------------+------------+-------------+-------------+
| Rx plain | accept | accept | accept | drop |
| (ACK|FIN|RST) | | | | |
+----------------+------------+------------+-------------+-------------+
| Rx PSP (good) | drop | accept | accept | accept |
+----------------+------------+------------+-------------+-------------+
| Rx PSP (bad | drop | drop | drop | drop |
| crypt, !=SPI) | | | | |
+----------------+------------+------------+-------------+-------------+
| Tx | plain text | plain text | encrypted | encrypted |
| | | | (excl. rtx) | (excl. rtx) |
+----------------+------------+------------+-------------+-------------+
To ensure that any data read from the socket after the ``tx-assoc``
call returns success has been authenticated, the kernel will scan the
receive and ofo queues of the socket at ``tx-assoc`` time. If any
enqueued packet was received in clear text, the Tx association will
fail, and the application should retry installing the Tx key after
draining the socket (this should not be necessary if both endpoints
are well behaved).
Because TCP sequence numbers are not integrity protected prior to
upgrading to PSP, it is possible that a MITM could offset sequence
numbers in a way that deletes a prefix of the PSP protected part of
the TCP stream. If userspace cares to mitigate this type of attack, a
special "start of PSP" message should be exchanged after ``tx-assoc``.
Rotation notifications
----------------------
The rotations of device key happen asynchronously and are usually
performed by management daemons, not under application control.
The PSP netlink family will generate a notification whenever keys
are rotated. The applications are expected to re-establish connections
before keys are rotated again.
Kernel implementation
=====================
Driver notes
------------
Drivers are expected to start with no PSP enabled (``psp-versions-ena``
in ``dev-get`` set to ``0``) whenever possible. The user space should
not depend on this behavior, as future extension may necessitate creation
of devices with PSP already enabled, nonetheless drivers should not enable
PSP by default. Enabling PSP should be the responsibility of the system
component which also takes care of key rotation.
Note that ``psp-versions-ena`` is expected to be used only for enabling
receive processing. The device is not expected to reject transmit requests
after ``psp-versions-ena`` has been disabled. User may also disable
``psp-versions-ena`` while there are active associations, which will
break all PSP Rx processing.
Drivers are expected to ensure that a device key is usable and secure
upon init, without explicit key rotation by the user space. It must be
possible to allocate working keys, and that no duplicate keys must be
generated. If the device allows the host to request the key for an
arbitrary SPI - driver should discard both device keys (rotate the
device key twice), to avoid potentially using a SPI+key which previous
OS instance already had access to.
Drivers must use ``psp_skb_get_assoc_rcu()`` to check if PSP Tx offload
was requested for given skb. On Rx drivers should allocate and populate
the ``SKB_EXT_PSP`` skb extension, and set the skb->decrypted bit to 1.
Kernel implementation notes
---------------------------
PSP implementation follows the TLS offload more closely than the IPsec
offload, with per-socket state, and the use of skb->decrypted to prevent
clear text leaks.
PSP device is separate from netdev, to make it possible to "delegate"
PSP offload capabilities to software devices (e.g. ``veth``).

View File

@ -437,8 +437,7 @@ message type supported. At run time this can be queried by means of the
RXRPC_SUPPORTED_CMSG socket option (see below).
==============
SOCKET OPTIONS
Socket Options
==============
AF_RXRPC sockets support a few socket options at the SOL_RXRPC level:
@ -495,8 +494,7 @@ AF_RXRPC sockets support a few socket options at the SOL_RXRPC level:
the highest control message type supported.
========
SECURITY
Security
========
Currently, only the kerberos 4 equivalent protocol has been implemented
@ -540,8 +538,7 @@ be found at:
http://people.redhat.com/~dhowells/rxrpc/listen.c
====================
EXAMPLE CLIENT USAGE
Example Client Usage
====================
A client would issue an operation by:

View File

@ -43,10 +43,19 @@ also point to the TCP header of the packet.
For IPv4 segmentation we support one of two types in terms of the IP ID.
The default behavior is to increment the IP ID with every segment. If the
GSO type SKB_GSO_TCP_FIXEDID is specified then we will not increment the IP
ID and all segments will use the same IP ID. If a device has
NETIF_F_TSO_MANGLEID set then the IP ID can be ignored when performing TSO
and we will either increment the IP ID for all frames, or leave it at a
static value based on driver preference.
ID and all segments will use the same IP ID.
For encapsulated packets, SKB_GSO_TCP_FIXEDID refers only to the outer header.
SKB_GSO_TCP_FIXEDID_INNER can be used to specify the same for the inner header.
Any combination of these two GSO types is allowed.
If a device has NETIF_F_TSO_MANGLEID set then the IP ID can be ignored when
performing TSO and we will either increment the IP ID for all frames, or leave
it at a static value based on driver preference. For encapsulated packets,
NETIF_F_TSO_MANGLEID is relevant for both outer and inner headers, unless the
DF bit is not set on the outer header, in which case the device driver must
guarantee that the IP ID field is incremented in the outer header with every
segment.
UDP Fragmentation Offload
@ -124,10 +133,7 @@ Generic Receive Offload
Generic receive offload is the complement to GSO. Ideally any frame
assembled by GRO should be segmented to create an identical sequence of
frames using GSO, and any sequence of frames segmented by GSO should be
able to be reassembled back to the original by GRO. The only exception to
this is IPv4 ID in the case that the DF bit is set for a given IP header.
If the value of the IPv4 ID is not sequentially incrementing it will be
altered so that it is when a frame assembled via GRO is segmented via GSO.
able to be reassembled back to the original by GRO.
Partial Generic Segmentation Offload

View File

@ -407,7 +407,7 @@ Clean-up patches
Netdev discourages patches which perform simple clean-ups, which are not in
the context of other work. For example:
* Addressing ``checkpatch.pl`` warnings
* Addressing ``checkpatch.pl``, and other trivial coding style warnings
* Addressing :ref:`Local variable ordering<rcs>` issues
* Conversions to device-managed APIs (``devm_`` helpers)

View File

@ -0,0 +1,123 @@
# SPDX-License-Identifier: GPL-2.0
# Copyright 2025 Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
"""
Sphinx extension for processing YAML files
"""
import os
import re
import sys
from pprint import pformat
from docutils import statemachine
from docutils.parsers.rst import Parser as RSTParser
from docutils.parsers.rst import states
from docutils.statemachine import ViewList
from sphinx.util import logging
from sphinx.parsers import Parser
srctree = os.path.abspath(os.environ["srctree"])
sys.path.insert(0, os.path.join(srctree, "tools/net/ynl/pyynl/lib"))
from doc_generator import YnlDocGenerator # pylint: disable=C0413
logger = logging.getLogger(__name__)
class YamlParser(Parser):
"""
Kernel parser for YAML files.
This is a simple sphinx.Parser to handle yaml files inside the
Kernel tree that will be part of the built documentation.
The actual parser function is not contained here: the code was
written in a way that parsing yaml for different subsystems
can be done from a single dispatcher.
All it takes to have parse YAML patches is to have an import line:
from some_parser_code import NewYamlGenerator
To this module. Then add an instance of the parser with:
new_parser = NewYamlGenerator()
and add a logic inside parse() to handle it based on the path,
like this:
if "/foo" in fname:
msg = self.new_parser.parse_yaml_file(fname)
"""
supported = ('yaml', )
netlink_parser = YnlDocGenerator()
re_lineno = re.compile(r"\.\. LINENO ([0-9]+)$")
tab_width = 8
def rst_parse(self, inputstring, document, msg):
"""
Receives a ReST content that was previously converted by the
YAML parser, adding it to the document tree.
"""
self.setup_parse(inputstring, document)
result = ViewList()
self.statemachine = states.RSTStateMachine(state_classes=states.state_classes,
initial_state='Body',
debug=document.reporter.debug_flag)
try:
# Parse message with RSTParser
lineoffset = 0;
lines = statemachine.string2lines(msg, self.tab_width,
convert_whitespace=True)
for line in lines:
match = self.re_lineno.match(line)
if match:
lineoffset = int(match.group(1))
continue
result.append(line, document.current_source, lineoffset)
self.statemachine.run(result, document)
except Exception as e:
document.reporter.error("YAML parsing error: %s" % pformat(e))
self.finish_parse()
# Overrides docutils.parsers.Parser. See sphinx.parsers.RSTParser
def parse(self, inputstring, document):
"""Check if a YAML is meant to be parsed."""
fname = document.current_source
# Handle netlink yaml specs
if "/netlink/specs/" in fname:
msg = self.netlink_parser.parse_yaml_file(fname)
self.rst_parse(inputstring, document, msg)
# All other yaml files are ignored
def setup(app):
"""Setup function for the Sphinx extension."""
# Add YAML parser
app.add_source_parser(YamlParser)
app.add_source_suffix('.yaml', 'yaml')
return {
'version': '1.0',
'parallel_read_safe': True,
'parallel_write_safe': True,
}

View File

@ -18,4 +18,4 @@ Netlink documentation for users.
See also:
- :ref:`Documentation/core-api/netlink.rst <kernel_netlink>`
- :ref:`Documentation/networking/netlink_spec/index.rst <specs>`
- :ref:`Documentation/netlink/specs/index.rst <specs>`

View File

@ -62,8 +62,8 @@ Sub-messages
------------
Several raw netlink families such as
:doc:`rt-link<../../networking/netlink_spec/rt-link>` and
:doc:`tc<../../networking/netlink_spec/tc>` use attribute nesting as an
:ref:`rt-link<netlink-rt-link>` and
:ref:`tc<netlink-tc>` use attribute nesting as an
abstraction to carry module specific information.
Conceptually it looks as follows::
@ -162,7 +162,7 @@ then this is an error.
Nested struct definitions
-------------------------
Many raw netlink families such as :doc:`tc<../../networking/netlink_spec/tc>`
Many raw netlink families such as :ref:`tc<netlink-tc>`
make use of nested struct definitions. The ``netlink-raw`` schema makes it
possible to embed a struct within a struct definition using the ``struct``
property. For example, the following struct definition embeds the

View File

@ -15,7 +15,7 @@ kernel headers directly.
Internally kernel uses the YAML specs to generate:
- the C uAPI header
- documentation of the protocol as a ReST file - see :ref:`Documentation/networking/netlink_spec/index.rst <specs>`
- documentation of the protocol as a ReST file - see :ref:`Documentation/netlink/specs/index.rst <specs>`
- policy tables for input attribute validation
- operation tables

View File

@ -1895,8 +1895,8 @@ M: Iyappan Subramanian <iyappan@os.amperecomputing.com>
M: Keyur Chudgar <keyur@os.amperecomputing.com>
M: Quan Nguyen <quan@os.amperecomputing.com>
S: Maintained
F: Documentation/devicetree/bindings/net/apm-xgene-enet.txt
F: Documentation/devicetree/bindings/net/apm-xgene-mdio.txt
F: Documentation/devicetree/bindings/net/apm,xgene-enet.yaml
F: Documentation/devicetree/bindings/net/apm,xgene-mdio-rgmii.yaml
F: drivers/net/ethernet/apm/xgene/
F: drivers/net/mdio/mdio-xgene.c
@ -5469,7 +5469,7 @@ F: net/sched/sch_cake.c
CAN NETWORK DRIVERS
M: Marc Kleine-Budde <mkl@pengutronix.de>
M: Vincent Mailhol <mailhol.vincent@wanadoo.fr>
M: Vincent Mailhol <mailhol@kernel.org>
L: linux-can@vger.kernel.org
S: Maintained
W: https://github.com/linux-can
@ -7205,6 +7205,13 @@ L: linux-gpio@vger.kernel.org
S: Maintained
F: drivers/gpio/gpio-gpio-mm.c
DIBS (DIRECT INTERNAL BUFFER SHARING)
M: Alexandra Winter <wintera@linux.ibm.com>
L: netdev@vger.kernel.org
S: Supported
F: drivers/dibs/
F: include/linux/dibs.h
DIGITEQ AUTOMOTIVE MGB4 V4L2 DRIVER
M: Martin Tuma <martin.tuma@digiteqautomotive.com>
L: linux-media@vger.kernel.org
@ -7382,6 +7389,7 @@ F: scripts/get_abi.py
F: scripts/kernel-doc*
F: scripts/lib/abi/*
F: scripts/lib/kdoc/*
F: tools/net/ynl/pyynl/lib/doc_generator.py
F: scripts/sphinx-pre-install
X: Documentation/ABI/
X: Documentation/admin-guide/media/
@ -9208,7 +9216,7 @@ S: Odd Fixes
F: drivers/net/ethernet/agere/
ETAS ES58X CAN/USB DRIVER
M: Vincent Mailhol <mailhol.vincent@wanadoo.fr>
M: Vincent Mailhol <mailhol@kernel.org>
L: linux-can@vger.kernel.org
S: Maintained
F: Documentation/networking/devlink/etas_es58x.rst
@ -9954,7 +9962,6 @@ F: drivers/net/ethernet/freescale/dpaa2/dpaa2-ptp*
F: drivers/net/ethernet/freescale/dpaa2/dprtc*
F: drivers/net/ethernet/freescale/enetc/enetc_ptp.c
F: drivers/ptp/ptp_qoriq.c
F: drivers/ptp/ptp_qoriq_debugfs.c
F: include/linux/fsl/ptp_qoriq.h
FREESCALE QUAD SPI DRIVER
@ -13970,8 +13977,7 @@ M: Hauke Mehrtens <hauke@hauke-m.de>
L: netdev@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml
F: drivers/net/dsa/lantiq_gswip.c
F: drivers/net/dsa/lantiq_pce.h
F: drivers/net/dsa/lantiq/*
F: drivers/net/ethernet/lantiq_xrx200.c
F: net/dsa/tag_gswip.c
@ -17771,7 +17777,6 @@ F: include/linux/fddidevice.h
F: include/linux/hippidevice.h
F: include/linux/if_*
F: include/linux/inetdevice.h
F: include/linux/ism.h
F: include/linux/netdev*
F: include/linux/platform_data/wiznet.h
F: include/uapi/linux/cn_proc.h
@ -18506,6 +18511,15 @@ F: Documentation/devicetree/bindings/clock/*imx*
F: drivers/clk/imx/
F: include/dt-bindings/clock/*imx*
NXP NETC TIMER PTP CLOCK DRIVER
M: Wei Fang <wei.fang@nxp.com>
M: Clark Wang <xiaoning.wang@nxp.com>
L: imx@lists.linux.dev
L: netdev@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/ptp/nxp,ptp-netc.yaml
F: drivers/ptp/ptp_netc.c
NXP PF5300/PF5301/PF5302 PMIC REGULATOR DEVICE DRIVER
M: Woodrow Douglass <wdouglass@carnegierobotics.com>
S: Maintained
@ -20917,6 +20931,13 @@ S: Maintained
F: Documentation/devicetree/bindings/net/qcom,bam-dmux.yaml
F: drivers/net/wwan/qcom_bam_dmux.c
QUALCOMM BLUETOOTH DRIVER
L: linux-arm-msm@vger.kernel.org
S: Maintained
F: drivers/bluetooth/btqca.[ch]
F: drivers/bluetooth/btqcomsmd.c
F: drivers/bluetooth/hci_qca.c
QUALCOMM CAMERA SUBSYSTEM DRIVER
M: Robert Foss <rfoss@kernel.org>
M: Todor Tomov <todor.too@gmail.com>
@ -21123,6 +21144,14 @@ S: Maintained
F: Documentation/devicetree/bindings/power/supply/qcom,pmi8998-charger.yaml
F: drivers/power/supply/qcom_smbx.c
QUALCOMM PPE DRIVER
M: Luo Jie <quic_luoj@quicinc.com>
L: netdev@vger.kernel.org
S: Supported
F: Documentation/devicetree/bindings/net/qcom,ipq9574-ppe.yaml
F: Documentation/networking/device_drivers/ethernet/qualcomm/ppe/ppe.rst
F: drivers/net/ethernet/qualcomm/ppe/
QUALCOMM QSEECOM DRIVER
M: Maximilian Luz <luzmaximilian@gmail.com>
L: linux-arm-msm@vger.kernel.org
@ -22484,7 +22513,6 @@ L: linux-s390@vger.kernel.org
L: netdev@vger.kernel.org
S: Supported
F: drivers/s390/net/
F: include/linux/ism.h
S390 PCI SUBSYSTEM
M: Niklas Schnelle <schnelle@linux.ibm.com>
@ -25584,6 +25612,18 @@ S: Maintained
F: Documentation/devicetree/bindings/net/ti,icss*.yaml
F: drivers/net/ethernet/ti/icssg/*
TI ICSSM ETHERNET DRIVER (ICSSM)
M: MD Danish Anwar <danishanwar@ti.com>
M: Parvathi Pudi <parvathi@couthit.com>
R: Roger Quadros <rogerq@kernel.org>
R: Mohan Reddy Putluru <pmohan@couthit.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
L: netdev@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/net/ti,icssm*.yaml
F: Documentation/devicetree/bindings/net/ti,pruss-ecap.yaml
F: drivers/net/ethernet/ti/icssm/*
TI J721E CSI2RX DRIVER
M: Jai Luthra <jai.luthra@linux.dev>
L: linux-media@vger.kernel.org

View File

@ -108,7 +108,7 @@ void __init config_BSP(char *commandp, int size)
* an ethernet switch. In this case we need to use the fixed phy type,
* and we need to declare it early in boot.
*/
static struct fixed_phy_status nettel_fixed_phy_status __initdata = {
static const struct fixed_phy_status nettel_fixed_phy_status __initconst = {
.link = 1,
.speed = 100,
.duplex = 0,
@ -119,7 +119,7 @@ static struct fixed_phy_status nettel_fixed_phy_status __initdata = {
static int __init init_BSP(void)
{
m5272_uarts_init();
fixed_phy_add(0, &nettel_fixed_phy_status);
fixed_phy_add(&nettel_fixed_phy_status);
clkdev_add_table(m5272_clk_lookup, ARRAY_SIZE(m5272_clk_lookup));
return 0;
}

View File

@ -256,7 +256,7 @@ static int __init bcm47xx_cpu_fixes(void)
}
arch_initcall(bcm47xx_cpu_fixes);
static struct fixed_phy_status bcm47xx_fixed_phy_status __initdata = {
static const struct fixed_phy_status bcm47xx_fixed_phy_status __initconst = {
.link = 1,
.speed = SPEED_100,
.duplex = DUPLEX_FULL,
@ -282,7 +282,7 @@ static int __init bcm47xx_register_bus_complete(void)
bcm47xx_leds_register();
bcm47xx_workarounds();
fixed_phy_add(0, &bcm47xx_fixed_phy_status);
fixed_phy_add(&bcm47xx_fixed_phy_status);
return 0;
}
device_initcall(bcm47xx_register_bus_complete);

View File

@ -11,6 +11,8 @@
compatible = "bananapi,bpi-f3", "spacemit,k1";
aliases {
ethernet0 = &eth0;
ethernet1 = &eth1;
serial0 = &uart0;
};
@ -40,6 +42,52 @@
status = "okay";
};
&eth0 {
phy-handle = <&rgmii0>;
phy-mode = "rgmii-id";
pinctrl-names = "default";
pinctrl-0 = <&gmac0_cfg>;
rx-internal-delay-ps = <0>;
tx-internal-delay-ps = <0>;
status = "okay";
mdio-bus {
#address-cells = <0x1>;
#size-cells = <0x0>;
reset-gpios = <&gpio K1_GPIO(110) GPIO_ACTIVE_LOW>;
reset-delay-us = <10000>;
reset-post-delay-us = <100000>;
rgmii0: phy@1 {
reg = <0x1>;
};
};
};
&eth1 {
phy-handle = <&rgmii1>;
phy-mode = "rgmii-id";
pinctrl-names = "default";
pinctrl-0 = <&gmac1_cfg>;
rx-internal-delay-ps = <0>;
tx-internal-delay-ps = <250>;
status = "okay";
mdio-bus {
#address-cells = <0x1>;
#size-cells = <0x0>;
reset-gpios = <&gpio K1_GPIO(115) GPIO_ACTIVE_LOW>;
reset-delay-us = <10000>;
reset-post-delay-us = <100000>;
rgmii1: phy@1 {
reg = <0x1>;
};
};
};
&pdma {
status = "okay";
};

View File

@ -12,6 +12,8 @@
compatible = "milkv,jupiter", "spacemit,k1";
aliases {
ethernet0 = &eth0;
ethernet1 = &eth1;
serial0 = &uart0;
};
@ -20,6 +22,52 @@
};
};
&eth0 {
phy-handle = <&rgmii0>;
phy-mode = "rgmii-id";
pinctrl-names = "default";
pinctrl-0 = <&gmac0_cfg>;
rx-internal-delay-ps = <0>;
tx-internal-delay-ps = <0>;
status = "okay";
mdio-bus {
#address-cells = <0x1>;
#size-cells = <0x0>;
reset-gpios = <&gpio K1_GPIO(110) GPIO_ACTIVE_LOW>;
reset-delay-us = <10000>;
reset-post-delay-us = <100000>;
rgmii0: phy@1 {
reg = <0x1>;
};
};
};
&eth1 {
phy-handle = <&rgmii1>;
phy-mode = "rgmii-id";
pinctrl-names = "default";
pinctrl-0 = <&gmac1_cfg>;
rx-internal-delay-ps = <0>;
tx-internal-delay-ps = <250>;
status = "okay";
mdio-bus {
#address-cells = <0x1>;
#size-cells = <0x0>;
reset-gpios = <&gpio K1_GPIO(115) GPIO_ACTIVE_LOW>;
reset-delay-us = <10000>;
reset-post-delay-us = <100000>;
rgmii1: phy@1 {
reg = <0x1>;
};
};
};
&pdma {
status = "okay";
};

View File

@ -11,6 +11,54 @@
#define K1_GPIO(x) (x / 32) (x % 32)
&pinctrl {
gmac0_cfg: gmac0-cfg {
gmac0-pins {
pinmux = <K1_PADCONF(0, 1)>, /* gmac0_rxdv */
<K1_PADCONF(1, 1)>, /* gmac0_rx_d0 */
<K1_PADCONF(2, 1)>, /* gmac0_rx_d1 */
<K1_PADCONF(3, 1)>, /* gmac0_rx_clk */
<K1_PADCONF(4, 1)>, /* gmac0_rx_d2 */
<K1_PADCONF(5, 1)>, /* gmac0_rx_d3 */
<K1_PADCONF(6, 1)>, /* gmac0_tx_d0 */
<K1_PADCONF(7, 1)>, /* gmac0_tx_d1 */
<K1_PADCONF(8, 1)>, /* gmac0_tx */
<K1_PADCONF(9, 1)>, /* gmac0_tx_d2 */
<K1_PADCONF(10, 1)>, /* gmac0_tx_d3 */
<K1_PADCONF(11, 1)>, /* gmac0_tx_en */
<K1_PADCONF(12, 1)>, /* gmac0_mdc */
<K1_PADCONF(13, 1)>, /* gmac0_mdio */
<K1_PADCONF(14, 1)>, /* gmac0_int_n */
<K1_PADCONF(45, 1)>; /* gmac0_clk_ref */
bias-pull-up = <0>;
drive-strength = <21>;
};
};
gmac1_cfg: gmac1-cfg {
gmac1-pins {
pinmux = <K1_PADCONF(29, 1)>, /* gmac1_rxdv */
<K1_PADCONF(30, 1)>, /* gmac1_rx_d0 */
<K1_PADCONF(31, 1)>, /* gmac1_rx_d1 */
<K1_PADCONF(32, 1)>, /* gmac1_rx_clk */
<K1_PADCONF(33, 1)>, /* gmac1_rx_d2 */
<K1_PADCONF(34, 1)>, /* gmac1_rx_d3 */
<K1_PADCONF(35, 1)>, /* gmac1_tx_d0 */
<K1_PADCONF(36, 1)>, /* gmac1_tx_d1 */
<K1_PADCONF(37, 1)>, /* gmac1_tx */
<K1_PADCONF(38, 1)>, /* gmac1_tx_d2 */
<K1_PADCONF(39, 1)>, /* gmac1_tx_d3 */
<K1_PADCONF(40, 1)>, /* gmac1_tx_en */
<K1_PADCONF(41, 1)>, /* gmac1_mdc */
<K1_PADCONF(42, 1)>, /* gmac1_mdio */
<K1_PADCONF(43, 1)>, /* gmac1_int_n */
<K1_PADCONF(46, 1)>; /* gmac1_clk_ref */
bias-pull-up = <0>;
drive-strength = <21>;
};
};
uart0_2_cfg: uart0-2-cfg {
uart0-2-pins {
pinmux = <K1_PADCONF(68, 2)>,

View File

@ -816,6 +816,28 @@
#size-cells = <2>;
dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>,
<0x0 0x80000000 0x1 0x00000000 0x0 0x80000000>;
eth0: ethernet@cac80000 {
compatible = "spacemit,k1-emac";
reg = <0x0 0xcac80000 0x0 0x420>;
clocks = <&syscon_apmu CLK_EMAC0_BUS>;
interrupts = <131>;
mac-address = [ 00 00 00 00 00 00 ];
resets = <&syscon_apmu RESET_EMAC0>;
spacemit,apmu = <&syscon_apmu 0x3e4>;
status = "disabled";
};
eth1: ethernet@cac81000 {
compatible = "spacemit,k1-emac";
reg = <0x0 0xcac81000 0x0 0x420>;
clocks = <&syscon_apmu CLK_EMAC1_BUS>;
interrupts = <133>;
mac-address = [ 00 00 00 00 00 00 ];
resets = <&syscon_apmu RESET_EMAC1>;
spacemit,apmu = <&syscon_apmu 0x3ec>;
status = "disabled";
};
};
pcie-bus {

View File

@ -125,8 +125,10 @@ CONFIG_XFRM_USER=m
CONFIG_NET_KEY=m
CONFIG_XDP_SOCKETS=y
CONFIG_XDP_SOCKETS_DIAG=m
CONFIG_DIBS=y
CONFIG_DIBS_LO=y
CONFIG_SMC=m
CONFIG_SMC_DIAG=m
CONFIG_SMC_LO=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_ADVANCED_ROUTER=y

View File

@ -116,8 +116,10 @@ CONFIG_XFRM_USER=m
CONFIG_NET_KEY=m
CONFIG_XDP_SOCKETS=y
CONFIG_XDP_SOCKETS_DIAG=m
CONFIG_DIBS=y
CONFIG_DIBS_LO=y
CONFIG_SMC=m
CONFIG_SMC_DIAG=m
CONFIG_SMC_LO=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_ADVANCED_ROUTER=y

View File

@ -195,4 +195,5 @@ obj-$(CONFIG_DRM_ACCEL) += accel/
obj-$(CONFIG_CDX_BUS) += cdx/
obj-$(CONFIG_DPLL) += dpll/
obj-$(CONFIG_DIBS) += dibs/
obj-$(CONFIG_S390) += s390/

View File

@ -20,7 +20,7 @@
#include <net/bluetooth/bluetooth.h>
#include <net/bluetooth/hci_core.h>
#include "h4_recv.h"
#include "hci_uart.h"
#define VERSION "0.11"

View File

@ -484,6 +484,7 @@ int btintel_version_info_tlv(struct hci_dev *hdev,
case 0x1d: /* BlazarU (BzrU) */
case 0x1e: /* BlazarI (Bzr) */
case 0x1f: /* Scorpious Peak */
case 0x22: /* BlazarIW (BzrIW) */
break;
default:
bt_dev_err(hdev, "Unsupported Intel hardware variant (0x%x)",
@ -3253,6 +3254,7 @@ void btintel_set_msft_opcode(struct hci_dev *hdev, u8 hw_variant)
case 0x1d:
case 0x1e:
case 0x1f:
case 0x22:
hci_set_msft_opcode(hdev, 0xFC1E);
break;
default:
@ -3593,6 +3595,7 @@ static int btintel_setup_combined(struct hci_dev *hdev)
case 0x1d:
case 0x1e:
case 0x1f:
case 0x22:
/* Display version information of TLV type */
btintel_version_info_tlv(hdev, &ver_tlv);

View File

@ -15,6 +15,7 @@
#include <linux/interrupt.h>
#include <linux/unaligned.h>
#include <linux/devcoredump.h>
#include <net/bluetooth/bluetooth.h>
#include <net/bluetooth/hci_core.h>
@ -35,8 +36,13 @@
/* Intel Bluetooth PCIe device id table */
static const struct pci_device_id btintel_pcie_table[] = {
/* BlazarI, Wildcat Lake */
{ BTINTEL_PCI_DEVICE(0x4D76, PCI_ANY_ID) },
/* BlazarI, Lunar Lake */
{ BTINTEL_PCI_DEVICE(0xA876, PCI_ANY_ID) },
/* Scorpious, Panther Lake-H484 */
{ BTINTEL_PCI_DEVICE(0xE376, PCI_ANY_ID) },
/* Scorpious, Panther Lake-H404 */
{ BTINTEL_PCI_DEVICE(0xE476, PCI_ANY_ID) },
{ 0 }
};
@ -554,25 +560,6 @@ static void btintel_pcie_mac_init(struct btintel_pcie_data *data)
btintel_pcie_wr_reg32(data, BTINTEL_PCIE_CSR_FUNC_CTRL_REG, reg);
}
static int btintel_pcie_add_dmp_data(struct hci_dev *hdev, const void *data, int size)
{
struct sk_buff *skb;
int err;
skb = alloc_skb(size, GFP_ATOMIC);
if (!skb)
return -ENOMEM;
skb_put_data(skb, data, size);
err = hci_devcd_append(hdev, skb);
if (err) {
bt_dev_err(hdev, "Failed to append data in the coredump");
return err;
}
return 0;
}
static int btintel_pcie_get_mac_access(struct btintel_pcie_data *data)
{
u32 reg;
@ -617,30 +604,35 @@ static void btintel_pcie_release_mac_access(struct btintel_pcie_data *data)
btintel_pcie_wr_reg32(data, BTINTEL_PCIE_CSR_FUNC_CTRL_REG, reg);
}
static void btintel_pcie_copy_tlv(struct sk_buff *skb, enum btintel_pcie_tlv_type type,
void *data, int size)
static void *btintel_pcie_copy_tlv(void *dest, enum btintel_pcie_tlv_type type,
void *data, size_t size)
{
struct intel_tlv *tlv;
tlv = skb_put(skb, sizeof(*tlv) + size);
tlv = dest;
tlv->type = type;
tlv->len = size;
memcpy(tlv->val, data, tlv->len);
return dest + sizeof(*tlv) + size;
}
static int btintel_pcie_read_dram_buffers(struct btintel_pcie_data *data)
{
u32 offset, prev_size, wr_ptr_status, dump_size, i;
u32 offset, prev_size, wr_ptr_status, dump_size, data_len;
struct btintel_pcie_dbgc *dbgc = &data->dbgc;
u8 buf_idx, dump_time_len, fw_build;
struct hci_dev *hdev = data->hdev;
u8 *pdata, *p, buf_idx;
struct intel_tlv *tlv;
struct timespec64 now;
struct sk_buff *skb;
struct tm tm_now;
char buf[256];
u16 hdr_len;
int ret;
char fw_build[128];
char ts[128];
char vendor[64];
char driver[64];
if (!IS_ENABLED(CONFIG_DEV_COREDUMP))
return -EOPNOTSUPP;
wr_ptr_status = btintel_pcie_rd_dev_mem(data, BTINTEL_PCIE_DBGC_CUR_DBGBUFF_STATUS);
offset = wr_ptr_status & BTINTEL_PCIE_DBG_OFFSET_BIT_MASK;
@ -657,88 +649,84 @@ static int btintel_pcie_read_dram_buffers(struct btintel_pcie_data *data)
else
return -EINVAL;
snprintf(vendor, sizeof(vendor), "Vendor: Intel\n");
snprintf(driver, sizeof(driver), "Driver: %s\n",
data->dmp_hdr.driver_name);
ktime_get_real_ts64(&now);
time64_to_tm(now.tv_sec, 0, &tm_now);
dump_time_len = snprintf(buf, sizeof(buf), "Dump Time: %02d-%02d-%04ld %02d:%02d:%02d",
snprintf(ts, sizeof(ts), "Dump Time: %02d-%02d-%04ld %02d:%02d:%02d",
tm_now.tm_mday, tm_now.tm_mon + 1, tm_now.tm_year + 1900,
tm_now.tm_hour, tm_now.tm_min, tm_now.tm_sec);
fw_build = snprintf(buf + dump_time_len, sizeof(buf) - dump_time_len,
snprintf(fw_build, sizeof(fw_build),
"Firmware Timestamp: Year %u WW %02u buildtype %u build %u",
2000 + (data->dmp_hdr.fw_timestamp >> 8),
data->dmp_hdr.fw_timestamp & 0xff, data->dmp_hdr.fw_build_type,
data->dmp_hdr.fw_build_num);
hdr_len = sizeof(*tlv) + sizeof(data->dmp_hdr.cnvi_bt) +
sizeof(*tlv) + sizeof(data->dmp_hdr.write_ptr) +
sizeof(*tlv) + sizeof(data->dmp_hdr.wrap_ctr) +
sizeof(*tlv) + sizeof(data->dmp_hdr.trigger_reason) +
sizeof(*tlv) + sizeof(data->dmp_hdr.fw_git_sha1) +
sizeof(*tlv) + sizeof(data->dmp_hdr.cnvr_top) +
sizeof(*tlv) + sizeof(data->dmp_hdr.cnvi_top) +
sizeof(*tlv) + dump_time_len +
sizeof(*tlv) + fw_build;
data_len = sizeof(*tlv) + sizeof(data->dmp_hdr.cnvi_bt) +
sizeof(*tlv) + sizeof(data->dmp_hdr.write_ptr) +
sizeof(*tlv) + sizeof(data->dmp_hdr.wrap_ctr) +
sizeof(*tlv) + sizeof(data->dmp_hdr.trigger_reason) +
sizeof(*tlv) + sizeof(data->dmp_hdr.fw_git_sha1) +
sizeof(*tlv) + sizeof(data->dmp_hdr.cnvr_top) +
sizeof(*tlv) + sizeof(data->dmp_hdr.cnvi_top) +
sizeof(*tlv) + strlen(ts) +
sizeof(*tlv) + strlen(fw_build) +
sizeof(*tlv) + strlen(vendor) +
sizeof(*tlv) + strlen(driver);
dump_size = hdr_len + sizeof(hdr_len);
/*
* sizeof(u32) - signature
* sizeof(data_len) - to store tlv data size
* data_len - TLV data
*/
dump_size = sizeof(u32) + sizeof(data_len) + data_len;
skb = alloc_skb(dump_size, GFP_KERNEL);
if (!skb)
return -ENOMEM;
/* Add debug buffers data length to dump size */
dump_size += BTINTEL_PCIE_DBGC_BUFFER_SIZE * dbgc->count;
ret = hci_devcd_init(hdev, dump_size);
if (ret) {
bt_dev_err(hdev, "Failed to init devcoredump, err %d", ret);
kfree_skb(skb);
return ret;
}
pdata = vmalloc(dump_size);
if (!pdata)
return -ENOMEM;
p = pdata;
skb_put_data(skb, &hdr_len, sizeof(hdr_len));
*(u32 *)p = BTINTEL_PCIE_MAGIC_NUM;
p += sizeof(u32);
btintel_pcie_copy_tlv(skb, BTINTEL_CNVI_BT, &data->dmp_hdr.cnvi_bt,
sizeof(data->dmp_hdr.cnvi_bt));
*(u32 *)p = data_len;
p += sizeof(u32);
btintel_pcie_copy_tlv(skb, BTINTEL_WRITE_PTR, &data->dmp_hdr.write_ptr,
sizeof(data->dmp_hdr.write_ptr));
p = btintel_pcie_copy_tlv(p, BTINTEL_VENDOR, vendor, strlen(vendor));
p = btintel_pcie_copy_tlv(p, BTINTEL_DRIVER, driver, strlen(driver));
p = btintel_pcie_copy_tlv(p, BTINTEL_DUMP_TIME, ts, strlen(ts));
p = btintel_pcie_copy_tlv(p, BTINTEL_FW_BUILD, fw_build,
strlen(fw_build));
p = btintel_pcie_copy_tlv(p, BTINTEL_CNVI_BT, &data->dmp_hdr.cnvi_bt,
sizeof(data->dmp_hdr.cnvi_bt));
p = btintel_pcie_copy_tlv(p, BTINTEL_WRITE_PTR, &data->dmp_hdr.write_ptr,
sizeof(data->dmp_hdr.write_ptr));
p = btintel_pcie_copy_tlv(p, BTINTEL_WRAP_CTR, &data->dmp_hdr.wrap_ctr,
sizeof(data->dmp_hdr.wrap_ctr));
data->dmp_hdr.wrap_ctr = btintel_pcie_rd_dev_mem(data,
BTINTEL_PCIE_DBGC_DBGBUFF_WRAP_ARND);
btintel_pcie_copy_tlv(skb, BTINTEL_WRAP_CTR, &data->dmp_hdr.wrap_ctr,
sizeof(data->dmp_hdr.wrap_ctr));
p = btintel_pcie_copy_tlv(p, BTINTEL_TRIGGER_REASON, &data->dmp_hdr.trigger_reason,
sizeof(data->dmp_hdr.trigger_reason));
p = btintel_pcie_copy_tlv(p, BTINTEL_FW_SHA, &data->dmp_hdr.fw_git_sha1,
sizeof(data->dmp_hdr.fw_git_sha1));
p = btintel_pcie_copy_tlv(p, BTINTEL_CNVR_TOP, &data->dmp_hdr.cnvr_top,
sizeof(data->dmp_hdr.cnvr_top));
p = btintel_pcie_copy_tlv(p, BTINTEL_CNVI_TOP, &data->dmp_hdr.cnvi_top,
sizeof(data->dmp_hdr.cnvi_top));
btintel_pcie_copy_tlv(skb, BTINTEL_TRIGGER_REASON, &data->dmp_hdr.trigger_reason,
sizeof(data->dmp_hdr.trigger_reason));
btintel_pcie_copy_tlv(skb, BTINTEL_FW_SHA, &data->dmp_hdr.fw_git_sha1,
sizeof(data->dmp_hdr.fw_git_sha1));
btintel_pcie_copy_tlv(skb, BTINTEL_CNVR_TOP, &data->dmp_hdr.cnvr_top,
sizeof(data->dmp_hdr.cnvr_top));
btintel_pcie_copy_tlv(skb, BTINTEL_CNVI_TOP, &data->dmp_hdr.cnvi_top,
sizeof(data->dmp_hdr.cnvi_top));
btintel_pcie_copy_tlv(skb, BTINTEL_DUMP_TIME, buf, dump_time_len);
btintel_pcie_copy_tlv(skb, BTINTEL_FW_BUILD, buf + dump_time_len, fw_build);
ret = hci_devcd_append(hdev, skb);
if (ret)
goto exit_err;
for (i = 0; i < dbgc->count; i++) {
ret = btintel_pcie_add_dmp_data(hdev, dbgc->bufs[i].data,
BTINTEL_PCIE_DBGC_BUFFER_SIZE);
if (ret)
break;
}
exit_err:
hci_devcd_complete(hdev);
return ret;
memcpy(p, dbgc->bufs[0].data, dbgc->count * BTINTEL_PCIE_DBGC_BUFFER_SIZE);
dev_coredumpv(&hdev->dev, pdata, dump_size, GFP_KERNEL);
return 0;
}
static void btintel_pcie_dump_traces(struct hci_dev *hdev)
@ -760,51 +748,6 @@ static void btintel_pcie_dump_traces(struct hci_dev *hdev)
bt_dev_err(hdev, "Failed to dump traces: (%d)", ret);
}
static void btintel_pcie_dump_hdr(struct hci_dev *hdev, struct sk_buff *skb)
{
struct btintel_pcie_data *data = hci_get_drvdata(hdev);
u16 len = skb->len;
u16 *hdrlen_ptr;
char buf[80];
hdrlen_ptr = skb_put_zero(skb, sizeof(len));
snprintf(buf, sizeof(buf), "Controller Name: 0x%X\n",
INTEL_HW_VARIANT(data->dmp_hdr.cnvi_bt));
skb_put_data(skb, buf, strlen(buf));
snprintf(buf, sizeof(buf), "Firmware Build Number: %u\n",
data->dmp_hdr.fw_build_num);
skb_put_data(skb, buf, strlen(buf));
snprintf(buf, sizeof(buf), "Driver: %s\n", data->dmp_hdr.driver_name);
skb_put_data(skb, buf, strlen(buf));
snprintf(buf, sizeof(buf), "Vendor: Intel\n");
skb_put_data(skb, buf, strlen(buf));
*hdrlen_ptr = skb->len - len;
}
static void btintel_pcie_dump_notify(struct hci_dev *hdev, int state)
{
struct btintel_pcie_data *data = hci_get_drvdata(hdev);
switch (state) {
case HCI_DEVCOREDUMP_IDLE:
data->dmp_hdr.state = HCI_DEVCOREDUMP_IDLE;
break;
case HCI_DEVCOREDUMP_ACTIVE:
data->dmp_hdr.state = HCI_DEVCOREDUMP_ACTIVE;
break;
case HCI_DEVCOREDUMP_TIMEOUT:
case HCI_DEVCOREDUMP_ABORT:
case HCI_DEVCOREDUMP_DONE:
data->dmp_hdr.state = HCI_DEVCOREDUMP_IDLE;
break;
}
}
/* This function enables BT function by setting BTINTEL_PCIE_CSR_FUNC_CTRL_MAC_INIT bit in
* BTINTEL_PCIE_CSR_FUNC_CTRL_REG register and wait for MSI-X with
* BTINTEL_PCIE_MSIX_HW_INT_CAUSES_GP0.
@ -1378,6 +1321,11 @@ static void btintel_pcie_rx_work(struct work_struct *work)
struct btintel_pcie_data, rx_work);
struct sk_buff *skb;
if (test_bit(BTINTEL_PCIE_COREDUMP_INPROGRESS, &data->flags)) {
btintel_pcie_dump_traces(data->hdev);
clear_bit(BTINTEL_PCIE_COREDUMP_INPROGRESS, &data->flags);
}
if (test_bit(BTINTEL_PCIE_HWEXP_INPROGRESS, &data->flags)) {
/* Unlike usb products, controller will not send hardware
* exception event on exception. Instead controller writes the
@ -1390,11 +1338,6 @@ static void btintel_pcie_rx_work(struct work_struct *work)
clear_bit(BTINTEL_PCIE_HWEXP_INPROGRESS, &data->flags);
}
if (test_bit(BTINTEL_PCIE_COREDUMP_INPROGRESS, &data->flags)) {
btintel_pcie_dump_traces(data->hdev);
clear_bit(BTINTEL_PCIE_COREDUMP_INPROGRESS, &data->flags);
}
/* Process the sk_buf in queue and send to the HCI layer */
while ((skb = skb_dequeue(&data->rx_skb_q))) {
btintel_pcie_recv_frame(data, skb);
@ -2149,6 +2092,7 @@ static int btintel_pcie_setup_internal(struct hci_dev *hdev)
switch (INTEL_HW_VARIANT(ver_tlv.cnvi_bt)) {
case 0x1e: /* BzrI */
case 0x1f: /* ScP */
case 0x22: /* BzrIW */
/* Display version information of TLV type */
btintel_version_info_tlv(hdev, &ver_tlv);
@ -2184,13 +2128,6 @@ static int btintel_pcie_setup_internal(struct hci_dev *hdev)
if (ver_tlv.img_type == 0x02 || ver_tlv.img_type == 0x03)
data->dmp_hdr.fw_git_sha1 = ver_tlv.git_sha1;
err = hci_devcd_register(hdev, btintel_pcie_dump_traces, btintel_pcie_dump_hdr,
btintel_pcie_dump_notify);
if (err) {
bt_dev_err(hdev, "Failed to register coredump (%d)", err);
goto exit_error;
}
btintel_print_fseq_info(hdev);
exit_error:
kfree_skb(skb);
@ -2236,6 +2173,7 @@ btintel_pcie_get_recovery(struct pci_dev *pdev, struct device *dev)
{
struct btintel_pcie_dev_recovery *tmp, *data = NULL;
const char *name = pci_name(pdev);
const size_t name_len = strlen(name) + 1;
struct hci_dev *hdev = to_hci_dev(dev);
spin_lock(&btintel_pcie_recovery_lock);
@ -2252,11 +2190,11 @@ btintel_pcie_get_recovery(struct pci_dev *pdev, struct device *dev)
return data;
}
data = kzalloc(struct_size(data, name, strlen(name) + 1), GFP_ATOMIC);
data = kzalloc(struct_size(data, name, name_len), GFP_ATOMIC);
if (!data)
return NULL;
strscpy_pad(data->name, name, strlen(name) + 1);
strscpy(data->name, name, name_len);
spin_lock(&btintel_pcie_recovery_lock);
list_add_tail(&data->list, &btintel_pcie_recovery_list);
spin_unlock(&btintel_pcie_recovery_lock);
@ -2319,7 +2257,6 @@ static void btintel_pcie_removal_work(struct work_struct *wk)
btintel_pcie_synchronize_irqs(data);
flush_work(&data->rx_work);
flush_work(&data->hdev->dump.dump_rx);
bt_dev_dbg(data->hdev, "Release bluetooth interface");
btintel_pcie_release_hdev(data);
@ -2410,6 +2347,13 @@ static void btintel_pcie_hw_error(struct hci_dev *hdev, u8 code)
btintel_pcie_reset(hdev);
}
static bool btintel_pcie_wakeup(struct hci_dev *hdev)
{
struct btintel_pcie_data *data = hci_get_drvdata(hdev);
return device_may_wakeup(&data->pdev->dev);
}
static int btintel_pcie_setup_hdev(struct btintel_pcie_data *data)
{
int err;
@ -2435,6 +2379,7 @@ static int btintel_pcie_setup_hdev(struct btintel_pcie_data *data)
hdev->set_diag = btintel_set_diag;
hdev->set_bdaddr = btintel_set_bdaddr;
hdev->reset = btintel_pcie_reset;
hdev->wakeup = btintel_pcie_wakeup;
err = hci_register_dev(hdev);
if (err < 0) {
@ -2573,11 +2518,100 @@ static void btintel_pcie_coredump(struct device *dev)
}
#endif
static int btintel_pcie_suspend_late(struct device *dev, pm_message_t mesg)
{
struct pci_dev *pdev = to_pci_dev(dev);
struct btintel_pcie_data *data;
ktime_t start;
u32 dxstate;
int err;
data = pci_get_drvdata(pdev);
dxstate = (mesg.event == PM_EVENT_SUSPEND ?
BTINTEL_PCIE_STATE_D3_HOT : BTINTEL_PCIE_STATE_D3_COLD);
data->gp0_received = false;
start = ktime_get();
/* Refer: 6.4.11.7 -> Platform power management */
btintel_pcie_wr_sleep_cntrl(data, dxstate);
err = wait_event_timeout(data->gp0_wait_q, data->gp0_received,
msecs_to_jiffies(BTINTEL_DEFAULT_INTR_TIMEOUT_MS));
if (err == 0) {
bt_dev_err(data->hdev,
"Timeout (%u ms) on alive interrupt for D3 entry",
BTINTEL_DEFAULT_INTR_TIMEOUT_MS);
return -EBUSY;
}
bt_dev_dbg(data->hdev,
"device entered into d3 state from d0 in %lld us",
ktime_to_us(ktime_get() - start));
return 0;
}
static int btintel_pcie_suspend(struct device *dev)
{
return btintel_pcie_suspend_late(dev, PMSG_SUSPEND);
}
static int btintel_pcie_hibernate(struct device *dev)
{
return btintel_pcie_suspend_late(dev, PMSG_HIBERNATE);
}
static int btintel_pcie_freeze(struct device *dev)
{
return btintel_pcie_suspend_late(dev, PMSG_FREEZE);
}
static int btintel_pcie_resume(struct device *dev)
{
struct pci_dev *pdev = to_pci_dev(dev);
struct btintel_pcie_data *data;
ktime_t start;
int err;
data = pci_get_drvdata(pdev);
data->gp0_received = false;
start = ktime_get();
/* Refer: 6.4.11.7 -> Platform power management */
btintel_pcie_wr_sleep_cntrl(data, BTINTEL_PCIE_STATE_D0);
err = wait_event_timeout(data->gp0_wait_q, data->gp0_received,
msecs_to_jiffies(BTINTEL_DEFAULT_INTR_TIMEOUT_MS));
if (err == 0) {
bt_dev_err(data->hdev,
"Timeout (%u ms) on alive interrupt for D0 entry",
BTINTEL_DEFAULT_INTR_TIMEOUT_MS);
return -EBUSY;
}
bt_dev_dbg(data->hdev,
"device entered into d0 state from d3 in %lld us",
ktime_to_us(ktime_get() - start));
return 0;
}
static const struct dev_pm_ops btintel_pcie_pm_ops = {
.suspend = btintel_pcie_suspend,
.resume = btintel_pcie_resume,
.freeze = btintel_pcie_freeze,
.thaw = btintel_pcie_resume,
.poweroff = btintel_pcie_hibernate,
.restore = btintel_pcie_resume,
};
static struct pci_driver btintel_pcie_driver = {
.name = KBUILD_MODNAME,
.id_table = btintel_pcie_table,
.probe = btintel_pcie_probe,
.remove = btintel_pcie_remove,
.driver.pm = pm_sleep_ptr(&btintel_pcie_pm_ops),
#ifdef CONFIG_DEV_COREDUMP
.driver.coredump = btintel_pcie_coredump
#endif

View File

@ -132,6 +132,8 @@ enum btintel_pcie_tlv_type {
BTINTEL_CNVI_TOP,
BTINTEL_DUMP_TIME,
BTINTEL_FW_BUILD,
BTINTEL_VENDOR,
BTINTEL_DRIVER
};
/* causes for the MBOX interrupts */

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