ALSA: sparc/dbri: Use guard() for spin locks
Clean up the code using guard() for spin locks. Merely code refactoring, and no behavior change. Signed-off-by: Takashi Iwai <tiwai@suse.de>
This commit is contained in:
Takashi Iwai
parent
4baca4bf86
commit
3c30d57544
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@ -758,40 +758,38 @@ static void dbri_initialize(struct snd_dbri *dbri)
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u32 dvma_addr = (u32)dbri->dma_dvma;
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s32 *cmd;
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u32 dma_addr;
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unsigned long flags;
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int n;
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spin_lock_irqsave(&dbri->lock, flags);
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scoped_guard(spinlock_irqsave, &dbri->lock) {
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dbri_reset(dbri);
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dbri_reset(dbri);
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/* Initialize pipes */
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for (n = 0; n < DBRI_NO_PIPES; n++)
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dbri->pipes[n].desc = dbri->pipes[n].first_desc = -1;
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/* Initialize pipes */
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for (n = 0; n < DBRI_NO_PIPES; n++)
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dbri->pipes[n].desc = dbri->pipes[n].first_desc = -1;
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spin_lock_init(&dbri->cmdlock);
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/*
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* Initialize the interrupt ring buffer.
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*/
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dma_addr = dvma_addr + dbri_dma_off(intr, 0);
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dbri->dma->intr[0] = dma_addr;
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dbri->dbri_irqp = 1;
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/*
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* Set up the interrupt queue
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*/
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scoped_guard(spinlock, &dbri->cmdlock) {
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cmd = dbri->cmdptr = dbri->dma->cmd;
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*(cmd++) = DBRI_CMD(D_IIQ, 0, 0);
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*(cmd++) = dma_addr;
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*(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
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dbri->cmdptr = cmd;
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*(cmd++) = DBRI_CMD(D_WAIT, 1, 0);
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*(cmd++) = DBRI_CMD(D_WAIT, 1, 0);
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dma_addr = dvma_addr + dbri_dma_off(cmd, 0);
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sbus_writel(dma_addr, dbri->regs + REG8);
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}
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}
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spin_lock_init(&dbri->cmdlock);
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/*
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* Initialize the interrupt ring buffer.
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*/
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dma_addr = dvma_addr + dbri_dma_off(intr, 0);
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dbri->dma->intr[0] = dma_addr;
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dbri->dbri_irqp = 1;
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/*
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* Set up the interrupt queue
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*/
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spin_lock(&dbri->cmdlock);
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cmd = dbri->cmdptr = dbri->dma->cmd;
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*(cmd++) = DBRI_CMD(D_IIQ, 0, 0);
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*(cmd++) = dma_addr;
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*(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
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dbri->cmdptr = cmd;
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*(cmd++) = DBRI_CMD(D_WAIT, 1, 0);
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*(cmd++) = DBRI_CMD(D_WAIT, 1, 0);
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dma_addr = dvma_addr + dbri_dma_off(cmd, 0);
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sbus_writel(dma_addr, dbri->regs + REG8);
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spin_unlock(&dbri->cmdlock);
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spin_unlock_irqrestore(&dbri->lock, flags);
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dbri_cmdwait(dbri);
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}
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@ -1002,7 +1000,6 @@ static void unlink_time_slot(struct snd_dbri *dbri, int pipe,
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static void xmit_fixed(struct snd_dbri *dbri, int pipe, unsigned int data)
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{
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s32 *cmd;
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unsigned long flags;
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if (pipe < 16 || pipe > DBRI_MAX_PIPE) {
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printk(KERN_ERR "DBRI: xmit_fixed: Illegal pipe number\n");
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@ -1037,9 +1034,10 @@ static void xmit_fixed(struct snd_dbri *dbri, int pipe, unsigned int data)
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*(cmd++) = data;
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*(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
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spin_lock_irqsave(&dbri->lock, flags);
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dbri_cmdsend(dbri, cmd, 3);
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spin_unlock_irqrestore(&dbri->lock, flags);
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scoped_guard(spinlock_irqsave, &dbri->lock) {
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dbri_cmdsend(dbri, cmd, 3);
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}
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dbri_cmdwait(dbri);
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}
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@ -1317,33 +1315,31 @@ to the DBRI via the CHI interface and few of the DBRI's PIO pins.
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*/
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static void cs4215_setup_pipes(struct snd_dbri *dbri)
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{
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unsigned long flags;
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scoped_guard(spinlock_irqsave, &dbri->lock) {
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/*
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* Data mode:
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* Pipe 4: Send timeslots 1-4 (audio data)
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* Pipe 20: Send timeslots 5-8 (part of ctrl data)
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* Pipe 6: Receive timeslots 1-4 (audio data)
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* Pipe 21: Receive timeslots 6-7. We can only receive 20 bits via
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* interrupt, and the rest of the data (slot 5 and 8) is
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* not relevant for us (only for doublechecking).
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*
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* Control mode:
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* Pipe 17: Send timeslots 1-4 (slots 5-8 are read only)
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* Pipe 18: Receive timeslot 1 (clb).
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* Pipe 19: Receive timeslot 7 (version).
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*/
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spin_lock_irqsave(&dbri->lock, flags);
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/*
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* Data mode:
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* Pipe 4: Send timeslots 1-4 (audio data)
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* Pipe 20: Send timeslots 5-8 (part of ctrl data)
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* Pipe 6: Receive timeslots 1-4 (audio data)
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* Pipe 21: Receive timeslots 6-7. We can only receive 20 bits via
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* interrupt, and the rest of the data (slot 5 and 8) is
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* not relevant for us (only for doublechecking).
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*
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* Control mode:
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* Pipe 17: Send timeslots 1-4 (slots 5-8 are read only)
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* Pipe 18: Receive timeslot 1 (clb).
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* Pipe 19: Receive timeslot 7 (version).
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*/
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setup_pipe(dbri, 4, D_SDP_MEM | D_SDP_TO_SER | D_SDP_MSB);
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setup_pipe(dbri, 20, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB);
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setup_pipe(dbri, 6, D_SDP_MEM | D_SDP_FROM_SER | D_SDP_MSB);
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setup_pipe(dbri, 21, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
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setup_pipe(dbri, 4, D_SDP_MEM | D_SDP_TO_SER | D_SDP_MSB);
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setup_pipe(dbri, 20, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB);
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setup_pipe(dbri, 6, D_SDP_MEM | D_SDP_FROM_SER | D_SDP_MSB);
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setup_pipe(dbri, 21, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
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setup_pipe(dbri, 17, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB);
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setup_pipe(dbri, 18, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
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setup_pipe(dbri, 19, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
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spin_unlock_irqrestore(&dbri->lock, flags);
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setup_pipe(dbri, 17, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB);
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setup_pipe(dbri, 18, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
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setup_pipe(dbri, 19, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
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}
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dbri_cmdwait(dbri);
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}
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@ -1418,7 +1414,6 @@ static void cs4215_open(struct snd_dbri *dbri)
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{
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int data_width;
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u32 tmp;
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unsigned long flags;
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dprintk(D_MM, "cs4215_open: %d channels, %d bits\n",
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dbri->mm.channels, dbri->mm.precision);
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@ -1443,35 +1438,35 @@ static void cs4215_open(struct snd_dbri *dbri)
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* bits. The CS4215, it seems, observes TSIN (the delayed signal)
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* even if it's the CHI master. Don't ask me...
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*/
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spin_lock_irqsave(&dbri->lock, flags);
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tmp = sbus_readl(dbri->regs + REG0);
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tmp &= ~(D_C); /* Disable CHI */
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sbus_writel(tmp, dbri->regs + REG0);
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scoped_guard(spinlock_irqsave, &dbri->lock) {
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tmp = sbus_readl(dbri->regs + REG0);
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tmp &= ~(D_C); /* Disable CHI */
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sbus_writel(tmp, dbri->regs + REG0);
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/* Switch CS4215 to data mode - set PIO3 to 1 */
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sbus_writel(D_ENPIO | D_PIO1 | D_PIO3 |
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(dbri->mm.onboard ? D_PIO0 : D_PIO2), dbri->regs + REG2);
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/* Switch CS4215 to data mode - set PIO3 to 1 */
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sbus_writel(D_ENPIO | D_PIO1 | D_PIO3 |
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(dbri->mm.onboard ? D_PIO0 : D_PIO2), dbri->regs + REG2);
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reset_chi(dbri, CHIslave, 128);
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reset_chi(dbri, CHIslave, 128);
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/* Note: this next doesn't work for 8-bit stereo, because the two
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* channels would be on timeslots 1 and 3, with 2 and 4 idle.
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* (See CS4215 datasheet Fig 15)
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*
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* DBRI non-contiguous mode would be required to make this work.
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*/
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data_width = dbri->mm.channels * dbri->mm.precision;
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/* Note: this next doesn't work for 8-bit stereo, because the two
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* channels would be on timeslots 1 and 3, with 2 and 4 idle.
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* (See CS4215 datasheet Fig 15)
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*
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* DBRI non-contiguous mode would be required to make this work.
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*/
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data_width = dbri->mm.channels * dbri->mm.precision;
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link_time_slot(dbri, 4, 16, 16, data_width, dbri->mm.offset);
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link_time_slot(dbri, 20, 4, 16, 32, dbri->mm.offset + 32);
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link_time_slot(dbri, 6, 16, 16, data_width, dbri->mm.offset);
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link_time_slot(dbri, 21, 6, 16, 16, dbri->mm.offset + 40);
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link_time_slot(dbri, 4, 16, 16, data_width, dbri->mm.offset);
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link_time_slot(dbri, 20, 4, 16, 32, dbri->mm.offset + 32);
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link_time_slot(dbri, 6, 16, 16, data_width, dbri->mm.offset);
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link_time_slot(dbri, 21, 6, 16, 16, dbri->mm.offset + 40);
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/* FIXME: enable CHI after _setdata? */
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tmp = sbus_readl(dbri->regs + REG0);
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tmp |= D_C; /* Enable CHI */
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sbus_writel(tmp, dbri->regs + REG0);
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spin_unlock_irqrestore(&dbri->lock, flags);
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/* FIXME: enable CHI after _setdata? */
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tmp = sbus_readl(dbri->regs + REG0);
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tmp |= D_C; /* Enable CHI */
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sbus_writel(tmp, dbri->regs + REG0);
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}
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cs4215_setdata(dbri, 0);
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}
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@ -1483,7 +1478,6 @@ static int cs4215_setctrl(struct snd_dbri *dbri)
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{
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int i, val;
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u32 tmp;
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unsigned long flags;
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/* FIXME - let the CPU do something useful during these delays */
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@ -1520,34 +1514,34 @@ static int cs4215_setctrl(struct snd_dbri *dbri)
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* done in hardware by a TI 248 that delays the DBRI->4215
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* frame sync signal by eight clock cycles. Anybody know why?
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*/
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spin_lock_irqsave(&dbri->lock, flags);
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tmp = sbus_readl(dbri->regs + REG0);
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tmp &= ~D_C; /* Disable CHI */
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sbus_writel(tmp, dbri->regs + REG0);
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scoped_guard(spinlock_irqsave, &dbri->lock) {
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tmp = sbus_readl(dbri->regs + REG0);
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tmp &= ~D_C; /* Disable CHI */
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sbus_writel(tmp, dbri->regs + REG0);
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reset_chi(dbri, CHImaster, 128);
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reset_chi(dbri, CHImaster, 128);
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/*
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* Control mode:
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* Pipe 17: Send timeslots 1-4 (slots 5-8 are read only)
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* Pipe 18: Receive timeslot 1 (clb).
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* Pipe 19: Receive timeslot 7 (version).
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*/
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/*
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* Control mode:
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* Pipe 17: Send timeslots 1-4 (slots 5-8 are read only)
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* Pipe 18: Receive timeslot 1 (clb).
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* Pipe 19: Receive timeslot 7 (version).
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*/
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link_time_slot(dbri, 17, 16, 16, 32, dbri->mm.offset);
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link_time_slot(dbri, 18, 16, 16, 8, dbri->mm.offset);
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link_time_slot(dbri, 19, 18, 16, 8, dbri->mm.offset + 48);
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spin_unlock_irqrestore(&dbri->lock, flags);
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link_time_slot(dbri, 17, 16, 16, 32, dbri->mm.offset);
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link_time_slot(dbri, 18, 16, 16, 8, dbri->mm.offset);
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link_time_slot(dbri, 19, 18, 16, 8, dbri->mm.offset + 48);
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}
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/* Wait for the chip to echo back CLB (Control Latch Bit) as zero */
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dbri->mm.ctrl[0] &= ~CS4215_CLB;
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xmit_fixed(dbri, 17, *(int *)dbri->mm.ctrl);
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spin_lock_irqsave(&dbri->lock, flags);
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tmp = sbus_readl(dbri->regs + REG0);
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tmp |= D_C; /* Enable CHI */
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sbus_writel(tmp, dbri->regs + REG0);
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spin_unlock_irqrestore(&dbri->lock, flags);
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scoped_guard(spinlock_irqsave, &dbri->lock) {
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tmp = sbus_readl(dbri->regs + REG0);
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tmp |= D_C; /* Enable CHI */
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sbus_writel(tmp, dbri->regs + REG0);
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}
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for (i = 10; ((dbri->mm.status & 0xe4) != 0x20); --i)
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msleep_interruptible(1);
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@ -1709,7 +1703,6 @@ static void xmit_descs(struct snd_dbri *dbri)
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struct dbri_streaminfo *info;
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u32 dvma_addr;
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s32 *cmd;
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unsigned long flags;
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int first_td;
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if (dbri == NULL)
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@ -1717,7 +1710,7 @@ static void xmit_descs(struct snd_dbri *dbri)
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dvma_addr = (u32)dbri->dma_dvma;
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info = &dbri->stream_info[DBRI_REC];
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spin_lock_irqsave(&dbri->lock, flags);
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guard(spinlock_irqsave)(&dbri->lock);
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if (info->pipe >= 0) {
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first_td = dbri->pipes[info->pipe].first_desc;
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@ -1760,8 +1753,6 @@ static void xmit_descs(struct snd_dbri *dbri)
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dbri->pipes[info->pipe].desc = first_td;
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}
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}
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spin_unlock_irqrestore(&dbri->lock, flags);
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}
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/* transmission_complete_intr()
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@ -1932,7 +1923,7 @@ static irqreturn_t snd_dbri_interrupt(int irq, void *dev_id)
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if (dbri == NULL)
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return IRQ_NONE;
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spin_lock(&dbri->lock);
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guard(spinlock)(&dbri->lock);
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/*
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* Read it, so the interrupt goes away.
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@ -1977,8 +1968,6 @@ static irqreturn_t snd_dbri_interrupt(int irq, void *dev_id)
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dbri_process_interrupt_buffer(dbri);
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spin_unlock(&dbri->lock);
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return IRQ_HANDLED;
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}
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@ -2046,17 +2035,16 @@ static int snd_dbri_open(struct snd_pcm_substream *substream)
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struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
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struct snd_pcm_runtime *runtime = substream->runtime;
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struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
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unsigned long flags;
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dprintk(D_USR, "open audio output.\n");
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runtime->hw = snd_dbri_pcm_hw;
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spin_lock_irqsave(&dbri->lock, flags);
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info->substream = substream;
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info->offset = 0;
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info->dvma_buffer = 0;
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info->pipe = -1;
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spin_unlock_irqrestore(&dbri->lock, flags);
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scoped_guard(spinlock_irqsave, &dbri->lock) {
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info->substream = substream;
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info->offset = 0;
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info->dvma_buffer = 0;
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info->pipe = -1;
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}
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snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
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snd_hw_rule_format, NULL, SNDRV_PCM_HW_PARAM_FORMAT,
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@ -2160,7 +2148,7 @@ static int snd_dbri_prepare(struct snd_pcm_substream *substream)
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else
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info->pipe = 6; /* Receive pipe */
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spin_lock_irq(&dbri->lock);
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guard(spinlock_irq)(&dbri->lock);
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info->offset = 0;
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/* Setup the all the transmit/receive descriptors to cover the
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@ -2169,8 +2157,6 @@ static int snd_dbri_prepare(struct snd_pcm_substream *substream)
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ret = setup_descs(dbri, DBRI_STREAMNO(substream),
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snd_pcm_lib_period_bytes(substream));
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spin_unlock_irq(&dbri->lock);
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dprintk(D_USR, "prepare audio output. %d bytes\n", info->size);
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return ret;
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}
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