drm/bridge: samsung-dsim: add driver support for exynos7870 DSIM bridge
Add support for Exynos7870's DSIM IP block in the bridge driver. Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org> Signed-off-by: Inki Dae <inki.dae@samsung.com>
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@ -244,6 +244,13 @@ static struct clk_bulk_data exynos5433_clk_bulk_data[] = {
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{ .id = "sclk_rgb_vclk_to_dsim0" },
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};
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static struct clk_bulk_data exynos7870_clk_bulk_data[] = {
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{ .id = "bus" },
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{ .id = "pll" },
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{ .id = "byte" },
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{ .id = "esc" },
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};
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enum reg_idx {
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DSIM_STATUS_REG, /* Status register (legacy) */
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DSIM_LINK_STATUS_REG, /* Link status register */
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@ -320,6 +327,32 @@ static const unsigned int exynos5433_reg_ofs[] = {
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[DSIM_PHYTIMING2_REG] = 0xBC,
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};
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static const unsigned int exynos7870_reg_ofs[] = {
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[DSIM_LINK_STATUS_REG] = 0x04,
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[DSIM_DPHY_STATUS_REG] = 0x08,
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[DSIM_SWRST_REG] = 0x0C,
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[DSIM_CLKCTRL_REG] = 0x10,
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[DSIM_TIMEOUT_REG] = 0x14,
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[DSIM_ESCMODE_REG] = 0x1C,
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[DSIM_MDRESOL_REG] = 0x20,
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[DSIM_MVPORCH_REG] = 0x24,
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[DSIM_MHPORCH_REG] = 0x28,
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[DSIM_MSYNC_REG] = 0x2C,
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[DSIM_CONFIG_REG] = 0x30,
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[DSIM_INTSRC_REG] = 0x34,
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[DSIM_INTMSK_REG] = 0x38,
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[DSIM_PKTHDR_REG] = 0x3C,
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[DSIM_PAYLOAD_REG] = 0x40,
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[DSIM_RXFIFO_REG] = 0x44,
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[DSIM_SFRCTRL_REG] = 0x48,
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[DSIM_FIFOCTRL_REG] = 0x4C,
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[DSIM_PLLCTRL_REG] = 0x94,
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[DSIM_PHYCTRL_REG] = 0xA4,
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[DSIM_PHYTIMING_REG] = 0xB4,
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[DSIM_PHYTIMING1_REG] = 0xB8,
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[DSIM_PHYTIMING2_REG] = 0xBC,
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};
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enum reg_value_idx {
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RESET_TYPE,
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PLL_TIMER,
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@ -392,6 +425,24 @@ static const unsigned int exynos5433_reg_values[] = {
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[PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0c),
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};
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static const unsigned int exynos7870_reg_values[] = {
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[RESET_TYPE] = DSIM_SWRST,
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[PLL_TIMER] = 80000,
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[STOP_STATE_CNT] = 0xa,
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[PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x177),
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[PHYCTRL_VREG_LP] = 0,
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[PHYCTRL_SLEW_UP] = 0,
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[PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x07),
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[PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0c),
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[PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x08),
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[PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x2b),
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[PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0d),
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[PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x09),
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[PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x09),
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[PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x0f),
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[PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0c),
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};
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static const unsigned int imx8mm_dsim_reg_values[] = {
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[RESET_TYPE] = DSIM_SWRST,
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[PLL_TIMER] = 500,
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@ -563,6 +614,36 @@ static const struct samsung_dsim_driver_data exynos5422_dsi_driver_data = {
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.min_freq = 500,
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};
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static const struct samsung_dsim_driver_data exynos7870_dsi_driver_data = {
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.reg_ofs = exynos7870_reg_ofs,
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.plltmr_reg = 0xa0,
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.has_clklane_stop = 1,
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.has_sfrctrl = 1,
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.clk_data = exynos7870_clk_bulk_data,
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.num_clks = ARRAY_SIZE(exynos7870_clk_bulk_data),
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.max_freq = 1500,
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.wait_for_hdr_fifo = 0,
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.wait_for_reset = 1,
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.num_bits_resol = 12,
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.video_mode_bit = 18,
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.pll_stable_bit = 24,
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.esc_clken_bit = 16,
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.byte_clken_bit = 17,
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.tx_req_hsclk_bit = 20,
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.lane_esc_clk_bit = 8,
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.lane_esc_data_offset = 9,
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.pll_p_offset = 13,
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.pll_m_offset = 3,
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.pll_s_offset = 0,
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.main_vsa_offset = 16,
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.reg_values = exynos7870_reg_values,
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.pll_fin_min = 6,
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.pll_fin_max = 12,
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.m_min = 41,
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.m_max = 125,
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.min_freq = 500,
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};
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static const struct samsung_dsim_driver_data imx8mm_dsi_driver_data = {
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.reg_ofs = exynos5433_reg_ofs,
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.plltmr_reg = 0xa0,
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@ -604,6 +685,7 @@ samsung_dsim_types[DSIM_TYPE_COUNT] = {
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[DSIM_TYPE_EXYNOS5410] = &exynos5_dsi_driver_data,
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[DSIM_TYPE_EXYNOS5422] = &exynos5422_dsi_driver_data,
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[DSIM_TYPE_EXYNOS5433] = &exynos5433_dsi_driver_data,
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[DSIM_TYPE_EXYNOS7870] = &exynos7870_dsi_driver_data,
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[DSIM_TYPE_IMX8MM] = &imx8mm_dsi_driver_data,
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[DSIM_TYPE_IMX8MP] = &imx8mm_dsi_driver_data,
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};
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@ -29,6 +29,7 @@ enum samsung_dsim_type {
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DSIM_TYPE_EXYNOS5410,
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DSIM_TYPE_EXYNOS5422,
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DSIM_TYPE_EXYNOS5433,
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DSIM_TYPE_EXYNOS7870,
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DSIM_TYPE_IMX8MM,
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DSIM_TYPE_IMX8MP,
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DSIM_TYPE_COUNT,
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