92 lines
3.9 KiB
C
92 lines
3.9 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright 2025 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef AMDGPU_UTILS_H_
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#define AMDGPU_UTILS_H_
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/* ---------- Generic 2‑bit capability attribute encoding ----------
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* 00 INVALID, 01 RO, 10 WO, 11 RW
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*/
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enum amdgpu_cap_attr {
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AMDGPU_CAP_ATTR_INVALID = 0,
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AMDGPU_CAP_ATTR_RO = 1 << 0,
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AMDGPU_CAP_ATTR_WO = 1 << 1,
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AMDGPU_CAP_ATTR_RW = (AMDGPU_CAP_ATTR_RO | AMDGPU_CAP_ATTR_WO),
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};
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#define AMDGPU_CAP_ATTR_BITS 2
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#define AMDGPU_CAP_ATTR_MAX ((1U << AMDGPU_CAP_ATTR_BITS) - 1)
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/* Internal helper to build helpers for a given enum NAME */
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#define DECLARE_ATTR_CAP_CLASS_HELPERS(NAME) \
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enum { NAME##_BITMAP_BITS = NAME##_COUNT * AMDGPU_CAP_ATTR_BITS }; \
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struct NAME##_caps { \
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DECLARE_BITMAP(bmap, NAME##_BITMAP_BITS); \
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}; \
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static inline unsigned int NAME##_ATTR_START(enum NAME##_cap_id cap) \
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{ return (unsigned int)cap * AMDGPU_CAP_ATTR_BITS; } \
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static inline void NAME##_attr_init(struct NAME##_caps *c) \
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{ if (c) bitmap_zero(c->bmap, NAME##_BITMAP_BITS); } \
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static inline int NAME##_attr_set(struct NAME##_caps *c, \
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enum NAME##_cap_id cap, enum amdgpu_cap_attr attr) \
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{ \
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if (!c) \
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return -EINVAL; \
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if (cap >= NAME##_COUNT) \
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return -EINVAL; \
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if ((unsigned int)attr > AMDGPU_CAP_ATTR_MAX) \
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return -EINVAL; \
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bitmap_write(c->bmap, (unsigned long)attr, \
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NAME##_ATTR_START(cap), AMDGPU_CAP_ATTR_BITS); \
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return 0; \
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} \
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static inline int NAME##_attr_get(const struct NAME##_caps *c, \
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enum NAME##_cap_id cap, enum amdgpu_cap_attr *out) \
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{ \
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unsigned long v; \
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if (!c || !out) \
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return -EINVAL; \
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if (cap >= NAME##_COUNT) \
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return -EINVAL; \
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v = bitmap_read(c->bmap, NAME##_ATTR_START(cap), AMDGPU_CAP_ATTR_BITS); \
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*out = (enum amdgpu_cap_attr)v; \
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return 0; \
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} \
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static inline bool NAME##_cap_is_ro(const struct NAME##_caps *c, enum NAME##_cap_id id) \
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{ enum amdgpu_cap_attr a; return !NAME##_attr_get(c, id, &a) && a == AMDGPU_CAP_ATTR_RO; } \
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static inline bool NAME##_cap_is_wo(const struct NAME##_caps *c, enum NAME##_cap_id id) \
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{ enum amdgpu_cap_attr a; return !NAME##_attr_get(c, id, &a) && a == AMDGPU_CAP_ATTR_WO; } \
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static inline bool NAME##_cap_is_rw(const struct NAME##_caps *c, enum NAME##_cap_id id) \
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{ enum amdgpu_cap_attr a; return !NAME##_attr_get(c, id, &a) && a == AMDGPU_CAP_ATTR_RW; }
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/* Element expander for enum creation */
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#define _CAP_ENUM_ELEM(x) x,
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/* Public macro: declare enum + helpers from an X‑macro list */
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#define DECLARE_ATTR_CAP_CLASS(NAME, LIST_MACRO) \
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enum NAME##_cap_id { LIST_MACRO(_CAP_ENUM_ELEM) NAME##_COUNT }; \
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DECLARE_ATTR_CAP_CLASS_HELPERS(NAME)
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#endif /* AMDGPU_UTILS_H_ */
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