217 lines
5.9 KiB
C
217 lines
5.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright IBM Corp. 1999,2013
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*
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* Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>,
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*
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* The description below was taken in large parts from the powerpc
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* bitops header file:
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* Within a word, bits are numbered LSB first. Lot's of places make
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* this assumption by directly testing bits with (val & (1<<nr)).
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* This can cause confusion for large (> 1 word) bitmaps on a
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* big-endian system because, unlike little endian, the number of each
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* bit depends on the word size.
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*
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* The bitop functions are defined to work on unsigned longs, so the bits
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* end up numbered:
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* |63..............0|127............64|191...........128|255...........192|
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*
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* We also have special functions which work with an MSB0 encoding.
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* The bits are numbered:
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* |0..............63|64............127|128...........191|192...........255|
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*
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* The main difference is that bit 0-63 in the bit number field needs to be
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* reversed compared to the LSB0 encoded bit fields. This can be achieved by
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* XOR with 0x3f.
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*
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*/
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#ifndef _S390_BITOPS_H
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#define _S390_BITOPS_H
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#ifndef _LINUX_BITOPS_H
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#error only <linux/bitops.h> can be included directly
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#endif
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#include <linux/typecheck.h>
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#include <linux/compiler.h>
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#include <linux/types.h>
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#include <asm/asm.h>
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#define arch___set_bit generic___set_bit
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#define arch___clear_bit generic___clear_bit
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#define arch___change_bit generic___change_bit
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#define arch___test_and_set_bit generic___test_and_set_bit
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#define arch___test_and_clear_bit generic___test_and_clear_bit
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#define arch___test_and_change_bit generic___test_and_change_bit
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#define arch_test_bit_acquire generic_test_bit_acquire
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static __always_inline bool arch_test_bit(unsigned long nr, const volatile unsigned long *ptr)
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{
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#ifdef __HAVE_ASM_FLAG_OUTPUTS__
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const volatile unsigned char *addr;
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unsigned long mask;
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int cc;
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/*
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* With CONFIG_PROFILE_ALL_BRANCHES enabled gcc fails to
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* handle __builtin_constant_p() in some cases.
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*/
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if (!IS_ENABLED(CONFIG_PROFILE_ALL_BRANCHES) && __builtin_constant_p(nr)) {
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addr = (const volatile unsigned char *)ptr;
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addr += (nr ^ (BITS_PER_LONG - BITS_PER_BYTE)) / BITS_PER_BYTE;
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mask = 1UL << (nr & (BITS_PER_BYTE - 1));
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asm volatile(
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" tm %[addr],%[mask]\n"
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: "=@cc" (cc)
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: [addr] "Q" (*addr), [mask] "I" (mask)
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);
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return cc == 3;
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}
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#endif
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return generic_test_bit(nr, ptr);
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}
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#include <asm-generic/bitops/atomic.h>
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#include <asm-generic/bitops/non-instrumented-non-atomic.h>
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#include <asm-generic/bitops/lock.h>
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/*
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* Functions which use MSB0 bit numbering.
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* The bits are numbered:
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* |0..............63|64............127|128...........191|192...........255|
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*/
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unsigned long find_first_bit_inv(const unsigned long *addr, unsigned long size);
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unsigned long find_next_bit_inv(const unsigned long *addr, unsigned long size,
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unsigned long offset);
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#define for_each_set_bit_inv(bit, addr, size) \
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for ((bit) = find_first_bit_inv((addr), (size)); \
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(bit) < (size); \
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(bit) = find_next_bit_inv((addr), (size), (bit) + 1))
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static inline void set_bit_inv(unsigned long nr, volatile unsigned long *ptr)
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{
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return set_bit(nr ^ (BITS_PER_LONG - 1), ptr);
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}
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static inline void clear_bit_inv(unsigned long nr, volatile unsigned long *ptr)
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{
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return clear_bit(nr ^ (BITS_PER_LONG - 1), ptr);
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}
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static inline bool test_and_clear_bit_inv(unsigned long nr,
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volatile unsigned long *ptr)
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{
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return test_and_clear_bit(nr ^ (BITS_PER_LONG - 1), ptr);
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}
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static inline void __set_bit_inv(unsigned long nr, volatile unsigned long *ptr)
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{
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return __set_bit(nr ^ (BITS_PER_LONG - 1), ptr);
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}
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static inline void __clear_bit_inv(unsigned long nr, volatile unsigned long *ptr)
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{
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return __clear_bit(nr ^ (BITS_PER_LONG - 1), ptr);
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}
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static inline bool test_bit_inv(unsigned long nr,
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const volatile unsigned long *ptr)
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{
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return test_bit(nr ^ (BITS_PER_LONG - 1), ptr);
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}
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#ifndef CONFIG_CC_HAS_BUILTIN_FFS
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/**
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* __flogr - find leftmost one
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* @word - The word to search
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*
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* Returns the bit number of the most significant bit set,
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* where the most significant bit has bit number 0.
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* If no bit is set this function returns 64.
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*/
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static __always_inline __attribute_const__ unsigned long __flogr(unsigned long word)
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{
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unsigned long bit;
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if (__builtin_constant_p(word)) {
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bit = 0;
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if (!word)
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return 64;
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if (!(word & 0xffffffff00000000UL)) {
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word <<= 32;
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bit += 32;
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}
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if (!(word & 0xffff000000000000UL)) {
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word <<= 16;
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bit += 16;
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}
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if (!(word & 0xff00000000000000UL)) {
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word <<= 8;
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bit += 8;
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}
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if (!(word & 0xf000000000000000UL)) {
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word <<= 4;
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bit += 4;
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}
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if (!(word & 0xc000000000000000UL)) {
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word <<= 2;
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bit += 2;
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}
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if (!(word & 0x8000000000000000UL)) {
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word <<= 1;
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bit += 1;
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}
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return bit;
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} else {
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union register_pair rp __uninitialized;
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rp.even = word;
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asm("flogr %[rp],%[rp]"
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: [rp] "+d" (rp.pair) : : "cc");
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bit = rp.even;
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/*
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* The result of the flogr instruction is a value in the range
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* of 0..64. Let the compiler know that the AND operation can
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* be optimized away.
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*/
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__assume(bit <= 64);
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return bit & 127;
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}
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}
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/**
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* ffs - find first bit set
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* @word: the word to search
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*
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* This is defined the same way as the libc and
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* compiler builtin ffs routines (man ffs).
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*/
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static __always_inline __flatten __attribute_const__ int ffs(int word)
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{
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unsigned int val = (unsigned int)word;
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return BITS_PER_LONG - __flogr(-val & val);
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}
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#else /* CONFIG_CC_HAS_BUILTIN_FFS */
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#include <asm-generic/bitops/builtin-ffs.h>
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#endif /* CONFIG_CC_HAS_BUILTIN_FFS */
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#include <asm-generic/bitops/builtin-__ffs.h>
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#include <asm-generic/bitops/ffz.h>
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#include <asm-generic/bitops/builtin-__fls.h>
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#include <asm-generic/bitops/builtin-fls.h>
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#include <asm-generic/bitops/fls64.h>
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#include <asm/arch_hweight.h>
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#include <asm-generic/bitops/const_hweight.h>
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#include <asm-generic/bitops/sched.h>
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#include <asm-generic/bitops/le.h>
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#include <asm-generic/bitops/ext2-atomic-setbit.h>
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#endif /* _S390_BITOPS_H */
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