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re PR target/66200 (GCC for ARM / AArch64 doesn't define TARGET_RELAXED_ORDERING) 

Fix PR target/66200

This applies the same fix for PR target/66200 for AArch64 on the GCC 5 branch
as on the 4.9 branch. On trunk we've fixed this differently by optimizing
the access to the guard variable using a load acquire style instruction.

2015-06-24  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>

	PR target/66200
	* g++.dg/abi/aarch64_guard1.C: Adjust.

2015-06-24  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>

	PR target/66200
	* configure.host (host_cpu): Add aarch64 case.
	* config/cpu/aarch64/atomic_word.h: New file.

From-SVN: r224890
This commit is contained in:
Ramana Radhakrishnan 2015-06-24 09:59:28 +00:00 committed by Ramana Radhakrishnan
parent 6379a523c4
commit 23fa65d6f3
6 changed files with 61 additions and 1 deletions
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3
gcc/config/aarch64/aarch64.c
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@ -11462,6 +11462,9 @@ aarch64_gen_adjusted_ldpstp (rtx *operands, bool load,
#undef TARGET_SCHED_FUSION_PRIORITY
#define TARGET_SCHED_FUSION_PRIORITY aarch64_sched_fusion_priority
#undef TARGET_RELAXED_ORDERING
#define TARGET_RELAXED_ORDERING true
struct gcc_target targetm = TARGET_INITIALIZER;
#include "gt-aarch64.h"

5
gcc/testsuite/ChangeLog
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@ -1,3 +1,8 @@
2015-06-24 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
PR target/66200
* g++.dg/abi/aarch64_guard1.C: Adjust.
2015-06-24 Mikael Morin <mikael@gcc.gnu.org>
PR fortran/66549

1
gcc/testsuite/g++.dg/abi/aarch64_guard1.C
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@ -13,5 +13,4 @@ int *foo ()
}
// { dg-final { scan-assembler _ZGVZ3foovE1x,8,8 } }
// { dg-final { scan-tree-dump "_ZGVZ3foovE1x & 1" "original" } }
// { dg-final { cleanup-tree-dump "original" } }

6
libstdc++-v3/ChangeLog
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@ -1,3 +1,9 @@
2015-06-24 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
PR target/66200
* configure.host (host_cpu): Add aarch64 case.
* config/cpu/aarch64/atomic_word.h: New file.
2015-06-22 Jonathan Wakely <jwakely@redhat.com>
Backport from mainline

44
libstdc++-v3/config/cpu/aarch64/atomic_word.h Normal file
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@ -0,0 +1,44 @@
// Low-level type for atomic operations -*- C++ -*-
// Copyright (C) 2015 Free Software Foundation, Inc.
//
// This file is part of the GNU ISO C++ Library. This library is free
// software; you can redistribute it and/or modify it under the
// terms of the GNU General Public License as published by the
// Free Software Foundation; either version 3, or (at your option)
// any later version.
// This library is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// Under Section 7 of GPL version 3, you are granted additional
// permissions described in the GCC Runtime Library Exception, version
// 3.1, as published by the Free Software Foundation.
// You should have received a copy of the GNU General Public License and
// a copy of the GCC Runtime Library Exception along with this program;
// see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
// <http://www.gnu.org/licenses/>.
/** @file atomic_word.h
* This file is a GNU extension to the Standard C++ Library.
*/
#ifndef _GLIBCXX_ATOMIC_WORD_H
#define _GLIBCXX_ATOMIC_WORD_H 1
typedef int _Atomic_word;
// This one prevents loads from being hoisted across the barrier;
// in other words, this is a Load-Load acquire barrier.
// This is necessary iff TARGET_RELAXED_ORDERING is defined in tm.h.
#define _GLIBCXX_READ_MEM_BARRIER __atomic_thread_fence (__ATOMIC_ACQUIRE)
// This one prevents stores from being sunk across the barrier; in other
// words, a Store-Store release barrier.
#define _GLIBCXX_WRITE_MEM_BARRIER __atomic_thread_fence (__ATOMIC_RELEASE)
#endif

3
libstdc++-v3/configure.host
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@ -153,6 +153,9 @@ esac
# Most can just use generic.
# THIS TABLE IS SORTED. KEEP IT THAT WAY.
case "${host_cpu}" in
aarch64*)
atomic_word_dir=cpu/aarch64
;;
alpha*)
atomic_word_dir=cpu/alpha
;;