mirror of git://gcc.gnu.org/git/gcc.git
config.gcc (hppa*-*-*): Remove MASK_BIG_SWITCH from CPU default.
* config.gcc (hppa*-*-*): Remove MASK_BIG_SWITCH from CPU default. * config/pa/pa.opt: Make mbig-switch a no-op. * config/pa/pa.h (TARGET_DEFAULT): Remove MASK_BIG_SWITCH. (CASE_VECTOR_MODE): Always return SImode. (ASM_OUTPUT_ADDR_VEC_ELT, ASM_OUTPUT_ADDR_DIFF_ELT): Remove code for the !TARGET_BIG_SWITCH case. * config/pa/pa-linux.h: Likewise. * config/pa/pa-openbsd.h: Likewise. * config/pa/pa-hpux.h: Define TARGET_DEFAULT to 0. * config/pa/pa.md (short_jump): Remove define_insn. (casesi): Remove code for the !TARGET_BIG_SWITCH case. (casesi0): Remove define_insn. (type): Remove btable_branch. (pa_combine_type): Likewise. (in_nullified_branch_delay): Likewise. (in_call_delay): Likewise. (define_delay): Likewise. (define_insn_reservation "Z3"): Likewise. (define_insn_reservation "Z4"): Likewise. * config/pa/pa.c (pa_reorg): Remove code for !TARGET_BIG_SWITCH. (pa_adjust_insn_length): Remove adjustment for btable branches. * doc/invoke.texi (HPPA Options): Delete documentation for mbig-switch and mno-big-switch Co-Authored-By: John David Anglin <dave.anglin@nrc-cnrc.gc.ca> From-SVN: r198612
This commit is contained in:
Steven Bosscher
John David Anglin
parent
3095685e6d
commit
33e6755738
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@ -1,3 +1,30 @@
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2013-05-05 Steven Bosscher <steven@gcc.gnu.org>
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John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
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* config.gcc (hppa*-*-*): Remove MASK_BIG_SWITCH from CPU default.
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* config/pa/pa.opt: Make mbig-switch a no-op.
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* config/pa/pa.h (TARGET_DEFAULT): Remove MASK_BIG_SWITCH.
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(CASE_VECTOR_MODE): Always return SImode.
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(ASM_OUTPUT_ADDR_VEC_ELT, ASM_OUTPUT_ADDR_DIFF_ELT): Remove code
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for the !TARGET_BIG_SWITCH case.
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* config/pa/pa-linux.h: Likewise.
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* config/pa/pa-openbsd.h: Likewise.
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* config/pa/pa-hpux.h: Define TARGET_DEFAULT to 0.
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* config/pa/pa.md (short_jump): Remove define_insn.
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(casesi): Remove code for the !TARGET_BIG_SWITCH case.
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(casesi0): Remove define_insn.
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(type): Remove btable_branch.
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(pa_combine_type): Likewise.
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(in_nullified_branch_delay): Likewise.
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(in_call_delay): Likewise.
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(define_delay): Likewise.
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(define_insn_reservation "Z3"): Likewise.
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(define_insn_reservation "Z4"): Likewise.
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* config/pa/pa.c (pa_reorg): Remove code for !TARGET_BIG_SWITCH.
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(pa_adjust_insn_length): Remove adjustment for btable branches.
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* doc/invoke.texi (HPPA Options): Delete documentation for mbig-switch
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and mno-big-switch
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2013-05-05 Uros Bizjak <ubizjak@gmail.com>
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* config/i386/sse.md (*vec_extract<ssevecmodelower>_0): Merge
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@ -3698,10 +3698,9 @@ case ${target} in
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;;
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hppa*-*-*)
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target_cpu_default2="MASK_BIG_SWITCH"
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if test x$gas = xyes
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then
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target_cpu_default2="${target_cpu_default2}|MASK_GAS|MASK_JUMP_IN_DELAY"
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target_cpu_default2="MASK_GAS|MASK_JUMP_IN_DELAY"
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fi
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;;
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@ -25,7 +25,7 @@ along with GCC; see the file COPYING3. If not see
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#define HPUX_LONG_DOUBLE_LIBRARY 1
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#undef TARGET_DEFAULT
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#define TARGET_DEFAULT MASK_BIG_SWITCH
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#define TARGET_DEFAULT 0
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/* Make GCC agree with types.h. */
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#undef SIZE_TYPE
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@ -78,17 +78,11 @@ along with GCC; see the file COPYING3. If not see
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#undef ASM_OUTPUT_ADDR_VEC_ELT
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#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
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if (TARGET_BIG_SWITCH) \
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fprintf (FILE, "\t.word .L%d\n", VALUE); \
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else \
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fprintf (FILE, "\tb .L%d\n\tnop\n", VALUE)
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fprintf (FILE, "\t.word .L%d\n", VALUE)
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#undef ASM_OUTPUT_ADDR_DIFF_ELT
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#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
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if (TARGET_BIG_SWITCH) \
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fprintf (FILE, "\t.word .L%d-.L%d\n", VALUE, REL); \
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else \
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fprintf (FILE, "\tb .L%d\n\tnop\n", VALUE)
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fprintf (FILE, "\t.word .L%d-.L%d\n", VALUE, REL)
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/* Use the default. */
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#undef ASM_OUTPUT_LABEL
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@ -49,17 +49,11 @@ along with GCC; see the file COPYING3. If not see
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#undef ASM_OUTPUT_ADDR_VEC_ELT
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#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
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if (TARGET_BIG_SWITCH) \
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fprintf (FILE, "\t.word .L%d\n", VALUE); \
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else \
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fprintf (FILE, "\tb .L%d\n\tnop\n", VALUE)
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fprintf (FILE, "\t.word .L%d\n", VALUE)
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#undef ASM_OUTPUT_ADDR_DIFF_ELT
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#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
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if (TARGET_BIG_SWITCH) \
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fprintf (FILE, "\t.word .L%d-.L%d\n", VALUE, REL); \
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else \
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fprintf (FILE, "\tb .L%d\n\tnop\n", VALUE)
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fprintf (FILE, "\t.word .L%d-.L%d\n", VALUE, REL)
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/* Use the default. */
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#undef ASM_OUTPUT_LABEL
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@ -4927,20 +4927,14 @@ pa_adjust_insn_length (rtx insn, int length)
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}
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}
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/* Jumps inside switch tables which have unfilled delay slots need
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adjustment. */
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if (JUMP_P (insn)
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&& GET_CODE (pat) == PARALLEL
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&& get_attr_type (insn) == TYPE_BTABLE_BRANCH)
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length += 4;
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/* Block move pattern. */
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else if (NONJUMP_INSN_P (insn)
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&& GET_CODE (pat) == PARALLEL
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&& GET_CODE (XVECEXP (pat, 0, 0)) == SET
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&& GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM
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&& GET_CODE (XEXP (XVECEXP (pat, 0, 0), 1)) == MEM
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&& GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode
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&& GET_MODE (XEXP (XVECEXP (pat, 0, 0), 1)) == BLKmode)
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if (NONJUMP_INSN_P (insn)
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&& GET_CODE (pat) == PARALLEL
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&& GET_CODE (XVECEXP (pat, 0, 0)) == SET
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&& GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM
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&& GET_CODE (XEXP (XVECEXP (pat, 0, 0), 1)) == MEM
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&& GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode
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&& GET_MODE (XEXP (XVECEXP (pat, 0, 0), 1)) == BLKmode)
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length += compute_movmem_length (insn) - 4;
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/* Block clear pattern. */
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else if (NONJUMP_INSN_P (insn)
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@ -8947,36 +8941,10 @@ pa_following_call (rtx insn)
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/* We use this hook to perform a PA specific optimization which is difficult
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to do in earlier passes.
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We want the delay slots of branches within jump tables to be filled.
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None of the compiler passes at the moment even has the notion that a
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PA jump table doesn't contain addresses, but instead contains actual
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instructions!
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Because we actually jump into the table, the addresses of each entry
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must stay constant in relation to the beginning of the table (which
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itself must stay constant relative to the instruction to jump into
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it). I don't believe we can guarantee earlier passes of the compiler
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will adhere to those rules.
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So, late in the compilation process we find all the jump tables, and
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expand them into real code -- e.g. each entry in the jump table vector
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will get an appropriate label followed by a jump to the final target.
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Reorg and the final jump pass can then optimize these branches and
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fill their delay slots. We end up with smaller, more efficient code.
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The jump instructions within the table are special; we must be able
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to identify them during assembly output (if the jumps don't get filled
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we need to emit a nop rather than nullifying the delay slot)). We
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identify jumps in switch tables by using insns with the attribute
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type TYPE_BTABLE_BRANCH.
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We also surround the jump table itself with BEGIN_BRTAB and END_BRTAB
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insns. This serves two purposes, first it prevents jump.c from
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noticing that the last N entries in the table jump to the instruction
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immediately after the table and deleting the jumps. Second, those
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insns mark where we should emit .begin_brtab and .end_brtab directives
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when using GAS (allows for better link time optimizations). */
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We surround the jump table itself with BEGIN_BRTAB and END_BRTAB
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insns. Those insns mark where we should emit .begin_brtab and
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.end_brtab directives when using GAS. This allows for better link
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time optimizations. */
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static void
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pa_reorg (void)
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@ -8988,83 +8956,23 @@ pa_reorg (void)
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if (pa_cpu < PROCESSOR_8000)
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pa_combine_instructions ();
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/* Still need brtab marker insns. FIXME: the presence of these
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markers disables output of the branch table to readonly memory,
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and any alignment directives that might be needed. Possibly,
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the begin_brtab insn should be output before the label for the
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table. This doesn't matter at the moment since the tables are
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always output in the text section. */
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for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
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{
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/* Find an ADDR_VEC insn. */
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if (! JUMP_TABLE_DATA_P (insn))
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continue;
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/* This is fairly cheap, so always run it if optimizing. */
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if (optimize > 0 && !TARGET_BIG_SWITCH)
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{
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/* Find and explode all ADDR_VEC or ADDR_DIFF_VEC insns. */
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for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
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{
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rtx pattern, tmp, location, label;
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unsigned int length, i;
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/* Find an ADDR_VEC or ADDR_DIFF_VEC insn to explode. */
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if (! JUMP_TABLE_DATA_P (insn))
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continue;
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/* Emit marker for the beginning of the branch table. */
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emit_insn_before (gen_begin_brtab (), insn);
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pattern = PATTERN (insn);
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location = PREV_INSN (insn);
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length = XVECLEN (pattern, GET_CODE (pattern) == ADDR_DIFF_VEC);
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for (i = 0; i < length; i++)
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{
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/* Emit a label before each jump to keep jump.c from
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removing this code. */
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tmp = gen_label_rtx ();
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LABEL_NUSES (tmp) = 1;
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emit_label_after (tmp, location);
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location = NEXT_INSN (location);
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if (GET_CODE (pattern) == ADDR_VEC)
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label = XEXP (XVECEXP (pattern, 0, i), 0);
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else
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label = XEXP (XVECEXP (pattern, 1, i), 0);
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tmp = gen_short_jump (label);
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/* Emit the jump itself. */
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tmp = emit_jump_insn_after (tmp, location);
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JUMP_LABEL (tmp) = label;
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LABEL_NUSES (label)++;
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location = NEXT_INSN (location);
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/* Emit a BARRIER after the jump. */
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emit_barrier_after (location);
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location = NEXT_INSN (location);
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}
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/* Emit marker for the end of the branch table. */
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emit_insn_before (gen_end_brtab (), location);
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location = NEXT_INSN (location);
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emit_barrier_after (location);
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/* Delete the ADDR_VEC or ADDR_DIFF_VEC. */
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delete_insn (insn);
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}
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}
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else
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{
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/* Still need brtab marker insns. FIXME: the presence of these
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markers disables output of the branch table to readonly memory,
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and any alignment directives that might be needed. Possibly,
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the begin_brtab insn should be output before the label for the
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table. This doesn't matter at the moment since the tables are
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always output in the text section. */
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for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
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{
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/* Find an ADDR_VEC insn. */
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if (! JUMP_TABLE_DATA_P (insn))
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continue;
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/* Now generate markers for the beginning and end of the
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branch table. */
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emit_insn_before (gen_begin_brtab (), insn);
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emit_insn_after (gen_end_brtab (), insn);
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}
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}
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/* Now generate markers for the beginning and end of the
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branch table. */
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emit_insn_before (gen_begin_brtab (), insn);
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emit_insn_after (gen_end_brtab (), insn);
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}
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}
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/* The PA has a number of odd instructions which can perform multiple
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@ -114,7 +114,7 @@ extern unsigned long total_code_bytes;
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#define TARGET_HPUX_UNWIND_LIBRARY 0
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#ifndef TARGET_DEFAULT
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#define TARGET_DEFAULT (MASK_GAS | MASK_JUMP_IN_DELAY | MASK_BIG_SWITCH)
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#define TARGET_DEFAULT (MASK_GAS | MASK_JUMP_IN_DELAY)
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#endif
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#ifndef TARGET_CPU_DEFAULT
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@ -984,11 +984,9 @@ do { \
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#define FUNCTION_NAME_P(NAME) (*(NAME) == '@')
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/* Specify the machine mode that this machine uses for the index in the
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tablejump instruction. For small tables, an element consists of a
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ia-relative branch and its delay slot. When -mbig-switch is specified,
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we use a 32-bit absolute address for non-pic code, and a 32-bit offset
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for both 32 and 64-bit pic code. */
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#define CASE_VECTOR_MODE (TARGET_BIG_SWITCH ? SImode : DImode)
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tablejump instruction. We use a 32-bit absolute address for non-pic code,
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and a 32-bit offset for 32 and 64-bit pic code. */
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#define CASE_VECTOR_MODE SImode
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/* Jump tables must be 32-bit aligned, no matter the size of the element. */
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#define ADDR_VEC_ALIGN(ADDR_VEC) 2
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@ -1165,13 +1163,16 @@ do { \
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pa_output_ascii ((FILE), (P), (SIZE))
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/* Jump tables are always placed in the text section. Technically, it
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is possible to put them in the readonly data section when -mbig-switch
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is specified. This has the benefit of getting the table out of .text
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and reducing branch lengths as a result. The downside is that an
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additional insn (addil) is needed to access the table when generating
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PIC code. The address difference table also has to use 32-bit
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pc-relative relocations. Currently, GAS does not support these
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relocations, although it is easily modified to do this operation.
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is possible to put them in the readonly data section. This has the
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benefit of getting the table out of .text and reducing branch lengths
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as a result.
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The downside is that an additional insn (addil) is needed to access
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the table when generating PIC code. The address difference table
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also has to use 32-bit pc-relative relocations. Currently, GAS does
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not support these relocations, although it is easily modified to do
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this operation.
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The table entries need to look like "$L1+(.+8-$L0)-$PIC_pcrel$0"
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when using ELF GAS. A simple difference can be used when using
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SOM GAS or the HP assembler. The final downside is GDB complains
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@ -1182,20 +1183,14 @@ do { \
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/* This is how to output an element of a case-vector that is absolute. */
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#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
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if (TARGET_BIG_SWITCH) \
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fprintf (FILE, "\t.word L$%04d\n", VALUE); \
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else \
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fprintf (FILE, "\tb L$%04d\n\tnop\n", VALUE)
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fprintf (FILE, "\t.word L$%04d\n", VALUE)
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/* This is how to output an element of a case-vector that is relative.
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Since we always place jump tables in the text section, the difference
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is absolute and requires no relocation. */
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#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
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if (TARGET_BIG_SWITCH) \
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fprintf (FILE, "\t.word L$%04d-L$%04d\n", VALUE, REL); \
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else \
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fprintf (FILE, "\tb L$%04d\n\tnop\n", VALUE)
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fprintf (FILE, "\t.word L$%04d-L$%04d\n", VALUE, REL)
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/* This is how to output an assembler line that says to advance the
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location counter to a multiple of 2**LOG bytes. */
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@ -123,7 +123,7 @@
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;; type "binary" insns have two input operands (1,2) and one output (0)
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(define_attr "type"
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"move,unary,binary,shift,nullshift,compare,load,store,uncond_branch,btable_branch,branch,cbranch,fbranch,call,sibcall,dyncall,fpload,fpstore,fpalu,fpcc,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,multi,milli,sh_func_adrs,parallel_branch,fpstore_load,store_fpload"
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"move,unary,binary,shift,nullshift,compare,load,store,uncond_branch,branch,cbranch,fbranch,call,sibcall,dyncall,fpload,fpstore,fpalu,fpcc,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,multi,milli,sh_func_adrs,parallel_branch,fpstore_load,store_fpload"
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(const_string "binary"))
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(define_attr "pa_combine_type"
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@ -166,7 +166,7 @@
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;; For conditional branches. Frame related instructions are not allowed
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;; because they confuse the unwind support.
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(define_attr "in_branch_delay" "false,true"
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(if_then_else (and (eq_attr "type" "!uncond_branch,btable_branch,branch,cbranch,fbranch,call,sibcall,dyncall,multi,milli,sh_func_adrs,parallel_branch")
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(if_then_else (and (eq_attr "type" "!uncond_branch,branch,cbranch,fbranch,call,sibcall,dyncall,multi,milli,sh_func_adrs,parallel_branch")
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(eq_attr "length" "4")
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(not (match_test "RTX_FRAME_RELATED_P (insn)")))
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(const_string "true")
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@ -175,7 +175,7 @@
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;; Disallow instructions which use the FPU since they will tie up the FPU
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;; even if the instruction is nullified.
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||||
(define_attr "in_nullified_branch_delay" "false,true"
|
||||
(if_then_else (and (eq_attr "type" "!uncond_branch,btable_branch,branch,cbranch,fbranch,call,sibcall,dyncall,multi,milli,sh_func_adrs,fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,parallel_branch")
|
||||
(if_then_else (and (eq_attr "type" "!uncond_branch,branch,cbranch,fbranch,call,sibcall,dyncall,multi,milli,sh_func_adrs,fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,parallel_branch")
|
||||
(eq_attr "length" "4")
|
||||
(not (match_test "RTX_FRAME_RELATED_P (insn)")))
|
||||
(const_string "true")
|
||||
|
|
@ -184,7 +184,7 @@
|
|||
;; For calls and millicode calls. Allow unconditional branches in the
|
||||
;; delay slot.
|
||||
(define_attr "in_call_delay" "false,true"
|
||||
(cond [(and (eq_attr "type" "!uncond_branch,btable_branch,branch,cbranch,fbranch,call,sibcall,dyncall,multi,milli,sh_func_adrs,parallel_branch")
|
||||
(cond [(and (eq_attr "type" "!uncond_branch,branch,cbranch,fbranch,call,sibcall,dyncall,multi,milli,sh_func_adrs,parallel_branch")
|
||||
(eq_attr "length" "4")
|
||||
(not (match_test "RTX_FRAME_RELATED_P (insn)")))
|
||||
(const_string "true")
|
||||
|
|
@ -208,7 +208,7 @@
|
|||
[(eq_attr "in_call_delay" "true") (nil) (nil)])
|
||||
|
||||
;; Return and other similar instructions.
|
||||
(define_delay (eq_attr "type" "btable_branch,branch,parallel_branch")
|
||||
(define_delay (eq_attr "type" "branch,parallel_branch")
|
||||
[(eq_attr "in_branch_delay" "true") (nil) (nil)])
|
||||
|
||||
;; Floating point conditional branch delay slot description.
|
||||
|
|
@ -657,7 +657,7 @@
|
|||
;; to assume have zero latency.
|
||||
(define_insn_reservation "Z3" 0
|
||||
(and
|
||||
(eq_attr "type" "!load,fpload,store,fpstore,uncond_branch,btable_branch,branch,cbranch,fbranch,call,sibcall,dyncall,multi,milli,sh_func_adrs,parallel_branch,fpcc,fpalu,fpmulsgl,fpmuldbl,fpsqrtsgl,fpsqrtdbl,fpdivsgl,fpdivdbl,fpstore_load,store_fpload")
|
||||
(eq_attr "type" "!load,fpload,store,fpstore,uncond_branch,branch,cbranch,fbranch,call,sibcall,dyncall,multi,milli,sh_func_adrs,parallel_branch,fpcc,fpalu,fpmulsgl,fpmuldbl,fpsqrtsgl,fpsqrtdbl,fpdivsgl,fpdivdbl,fpstore_load,store_fpload")
|
||||
(eq_attr "cpu" "8000"))
|
||||
"inm_8000,rnm_8000")
|
||||
|
||||
|
|
@ -665,7 +665,7 @@
|
|||
;; retirement unit.
|
||||
(define_insn_reservation "Z4" 0
|
||||
(and
|
||||
(eq_attr "type" "uncond_branch,btable_branch,branch,cbranch,fbranch,call,sibcall,dyncall,multi,milli,sh_func_adrs,parallel_branch")
|
||||
(eq_attr "type" "uncond_branch,branch,cbranch,fbranch,call,sibcall,dyncall,multi,milli,sh_func_adrs,parallel_branch")
|
||||
(eq_attr "cpu" "8000"))
|
||||
"inm0_8000+inm1_8000,rnm0_8000+rnm1_8000")
|
||||
|
||||
|
|
@ -6959,16 +6959,6 @@
|
|||
[(set_attr "type" "branch")
|
||||
(set_attr "length" "4")])
|
||||
|
||||
;;; This jump is used in branch tables where the insn length is fixed.
|
||||
;;; The length of this insn is adjusted if the delay slot is not filled.
|
||||
(define_insn "short_jump"
|
||||
[(set (pc) (label_ref (match_operand 0 "" "")))
|
||||
(const_int 0)]
|
||||
""
|
||||
"b%* %l0%#"
|
||||
[(set_attr "type" "btable_branch")
|
||||
(set_attr "length" "4")])
|
||||
|
||||
;; Subroutines of "casesi".
|
||||
;; operand 0 is index
|
||||
;; operand 1 is the minimum bound
|
||||
|
|
@ -7028,34 +7018,15 @@
|
|||
operands[0] = index;
|
||||
}
|
||||
|
||||
if (TARGET_BIG_SWITCH)
|
||||
{
|
||||
if (TARGET_64BIT)
|
||||
emit_jump_insn (gen_casesi64p (operands[0], operands[3]));
|
||||
else if (flag_pic)
|
||||
emit_jump_insn (gen_casesi32p (operands[0], operands[3]));
|
||||
else
|
||||
emit_jump_insn (gen_casesi32 (operands[0], operands[3]));
|
||||
}
|
||||
if (TARGET_64BIT)
|
||||
emit_jump_insn (gen_casesi64p (operands[0], operands[3]));
|
||||
else if (flag_pic)
|
||||
emit_jump_insn (gen_casesi32p (operands[0], operands[3]));
|
||||
else
|
||||
emit_jump_insn (gen_casesi0 (operands[0], operands[3]));
|
||||
emit_jump_insn (gen_casesi32 (operands[0], operands[3]));
|
||||
DONE;
|
||||
}")
|
||||
|
||||
;;; The rtl for this pattern doesn't accurately describe what the insn
|
||||
;;; actually does, particularly when case-vector elements are exploded
|
||||
;;; in pa_reorg. However, the initial SET in these patterns must show
|
||||
;;; the connection of the insn to the following jump table.
|
||||
(define_insn "casesi0"
|
||||
[(set (pc) (mem:SI (plus:SI
|
||||
(mult:SI (match_operand:SI 0 "register_operand" "r")
|
||||
(const_int 4))
|
||||
(label_ref (match_operand 1 "" "")))))]
|
||||
""
|
||||
"blr,n %0,%%r0\;nop"
|
||||
[(set_attr "type" "multi")
|
||||
(set_attr "length" "8")])
|
||||
|
||||
;;; 32-bit code, absolute branch table.
|
||||
(define_insn "casesi32"
|
||||
[(set (pc) (mem:SI (plus:SI
|
||||
|
|
|
|||
|
|
@ -38,8 +38,8 @@ Target RejectNegative
|
|||
Generate PA2.0 code (requires binutils 2.10 or later)
|
||||
|
||||
mbig-switch
|
||||
Target Report Mask(BIG_SWITCH)
|
||||
Generate code for huge switch statements
|
||||
Target Ignore
|
||||
Does nothing. Preserved for backward compatibility.
|
||||
|
||||
mdisable-fpregs
|
||||
Target Report Mask(DISABLE_FPREGS)
|
||||
|
|
|
|||
|
|
@ -618,11 +618,11 @@ Objective-C and Objective-C++ Dialects}.
|
|||
|
||||
@emph{HPPA Options}
|
||||
@gccoptlist{-march=@var{architecture-type} @gol
|
||||
-mbig-switch -mdisable-fpregs -mdisable-indexing @gol
|
||||
-mdisable-fpregs -mdisable-indexing @gol
|
||||
-mfast-indirect-calls -mgas -mgnu-ld -mhp-ld @gol
|
||||
-mfixed-range=@var{register-range} @gol
|
||||
-mjump-in-delay -mlinker-opt -mlong-calls @gol
|
||||
-mlong-load-store -mno-big-switch -mno-disable-fpregs @gol
|
||||
-mlong-load-store -mno-disable-fpregs @gol
|
||||
-mno-disable-indexing -mno-fast-indirect-calls -mno-gas @gol
|
||||
-mno-jump-in-delay -mno-long-load-store @gol
|
||||
-mno-portable-runtime -mno-soft-float @gol
|
||||
|
|
@ -13510,12 +13510,6 @@ other way around.
|
|||
@opindex mpa-risc-2-0
|
||||
Synonyms for @option{-march=1.0}, @option{-march=1.1}, and @option{-march=2.0} respectively.
|
||||
|
||||
@item -mbig-switch
|
||||
@opindex mbig-switch
|
||||
Generate code suitable for big switch tables. Use this option only if
|
||||
the assembler/linker complain about out-of-range branches within a switch
|
||||
table.
|
||||
|
||||
@item -mjump-in-delay
|
||||
@opindex mjump-in-delay
|
||||
Fill delay slots of function calls with unconditional jump instructions
|
||||
|
|
|
|||
Loading…
Reference in New Issue