mirror of git://gcc.gnu.org/git/gcc.git
s390.c (Z10_PREDICT_DISTANCE): New macro.
2009-08-20 Andreas Krebbel <krebbel1@de.ibm.com> * config/s390/s390.c (Z10_PREDICT_DISTANCE): New macro. (s390_z10_fix_long_loop_prediction): New function. (s390_z10_optimize_cmp): INSN walk moved to callee - s390_reorg. (s390_reorg): Walk over the INSNs and invoke s390_z10_fix_long_loop_prediction and s390_z10_optimize_cmp. From-SVN: r150955
This commit is contained in:
Andreas Krebbel
Andreas Krebbel
parent
f114923514
commit
b0f86a7e6b
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@ -1,3 +1,11 @@
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2009-08-20 Andreas Krebbel <krebbel1@de.ibm.com>
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* config/s390/s390.c (Z10_PREDICT_DISTANCE): New macro.
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(s390_z10_fix_long_loop_prediction): New function.
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(s390_z10_optimize_cmp): INSN walk moved to callee - s390_reorg.
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(s390_reorg): Walk over the INSNs and invoke
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s390_z10_fix_long_loop_prediction and s390_z10_optimize_cmp.
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2009-08-20 Andreas Krebbel <krebbel1@de.ibm.com>
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2009-08-20 Andreas Krebbel <krebbel1@de.ibm.com>
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* config/s390/s390.md ("*brx_stage1_<GPR:mode>", "*brxg_64bit",
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* config/s390/s390.md ("*brx_stage1_<GPR:mode>", "*brxg_64bit",
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@ -345,6 +345,10 @@ struct GTY(()) machine_function
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#define REGNO_PAIR_OK(REGNO, MODE) \
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#define REGNO_PAIR_OK(REGNO, MODE) \
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(HARD_REGNO_NREGS ((REGNO), (MODE)) == 1 || !((REGNO) & 1))
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(HARD_REGNO_NREGS ((REGNO), (MODE)) == 1 || !((REGNO) & 1))
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/* That's the read ahead of the dynamic branch prediction unit in
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bytes on a z10 CPU. */
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#define Z10_PREDICT_DISTANCE 384
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static enum machine_mode
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static enum machine_mode
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s390_libgcc_cmp_return_mode (void)
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s390_libgcc_cmp_return_mode (void)
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{
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{
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@ -9661,6 +9665,66 @@ s390_optimize_prologue (void)
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}
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}
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}
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}
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/* On z10 the dynamic branch prediction must see the backward jump in
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a window of 384 bytes. If not it falls back to the static
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prediction. This function rearranges the loop backward branch in a
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way which makes the static prediction always correct. The function
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returns true if it added an instruction. */
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static bool
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s390_z10_fix_long_loop_prediction (rtx insn)
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{
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rtx set = single_set (insn);
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rtx code_label, label_ref, new_label;
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rtx uncond_jump;
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rtx cur_insn;
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rtx tmp;
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int distance;
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/* This will exclude branch on count and branch on index patterns
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since these are correctly statically predicted. */
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if (!set
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|| SET_DEST (set) != pc_rtx
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|| GET_CODE (SET_SRC(set)) != IF_THEN_ELSE)
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return false;
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label_ref = (GET_CODE (XEXP (SET_SRC (set), 1)) == LABEL_REF ?
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XEXP (SET_SRC (set), 1) : XEXP (SET_SRC (set), 2));
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gcc_assert (GET_CODE (label_ref) == LABEL_REF);
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code_label = XEXP (label_ref, 0);
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if (INSN_ADDRESSES (INSN_UID (code_label)) == -1
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|| INSN_ADDRESSES (INSN_UID (insn)) == -1
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|| (INSN_ADDRESSES (INSN_UID (insn))
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- INSN_ADDRESSES (INSN_UID (code_label)) < Z10_PREDICT_DISTANCE))
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return false;
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for (distance = 0, cur_insn = PREV_INSN (insn);
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distance < Z10_PREDICT_DISTANCE - 6;
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distance += get_attr_length (cur_insn), cur_insn = PREV_INSN (cur_insn))
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if (!cur_insn || JUMP_P (cur_insn) || LABEL_P (cur_insn))
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return false;
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new_label = gen_label_rtx ();
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uncond_jump = emit_jump_insn_after (
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gen_rtx_SET (VOIDmode, pc_rtx,
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gen_rtx_LABEL_REF (VOIDmode, code_label)),
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insn);
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emit_label_after (new_label, uncond_jump);
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tmp = XEXP (SET_SRC (set), 1);
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XEXP (SET_SRC (set), 1) = XEXP (SET_SRC (set), 2);
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XEXP (SET_SRC (set), 2) = tmp;
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INSN_CODE (insn) = -1;
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XEXP (label_ref, 0) = new_label;
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JUMP_LABEL (insn) = new_label;
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JUMP_LABEL (uncond_jump) = code_label;
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return true;
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}
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/* Returns 1 if INSN reads the value of REG for purposes not related
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/* Returns 1 if INSN reads the value of REG for purposes not related
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to addressing of memory, and 0 otherwise. */
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to addressing of memory, and 0 otherwise. */
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static int
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static int
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@ -9743,97 +9807,87 @@ s390_swap_cmp (rtx cond, rtx *op0, rtx *op1, rtx insn)
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if that register's value is delivered via a bypass, then the
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if that register's value is delivered via a bypass, then the
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pipeline recycles, thereby causing significant performance decline.
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pipeline recycles, thereby causing significant performance decline.
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This function locates such situations and exchanges the two
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This function locates such situations and exchanges the two
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operands of the compare. */
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operands of the compare. The function return true whenever it
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static void
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added an insn. */
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s390_z10_optimize_cmp (void)
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static bool
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s390_z10_optimize_cmp (rtx insn)
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{
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{
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rtx insn, prev_insn, next_insn;
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rtx prev_insn, next_insn;
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int added_NOPs = 0;
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bool insn_added_p = false;
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rtx cond, *op0, *op1;
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for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
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if (GET_CODE (PATTERN (insn)) == PARALLEL)
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{
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{
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rtx cond, *op0, *op1;
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/* Handle compare and branch and branch on count
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instructions. */
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rtx pattern = single_set (insn);
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if (!INSN_P (insn) || INSN_CODE (insn) <= 0)
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if (!pattern
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continue;
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|| SET_DEST (pattern) != pc_rtx
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|| GET_CODE (SET_SRC (pattern)) != IF_THEN_ELSE)
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return false;
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if (GET_CODE (PATTERN (insn)) == PARALLEL)
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cond = XEXP (SET_SRC (pattern), 0);
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op0 = &XEXP (cond, 0);
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op1 = &XEXP (cond, 1);
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}
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else if (GET_CODE (PATTERN (insn)) == SET)
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{
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rtx src, dest;
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/* Handle normal compare instructions. */
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src = SET_SRC (PATTERN (insn));
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dest = SET_DEST (PATTERN (insn));
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if (!REG_P (dest)
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|| !CC_REGNO_P (REGNO (dest))
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|| GET_CODE (src) != COMPARE)
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return false;
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/* s390_swap_cmp will try to find the conditional
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jump when passing NULL_RTX as condition. */
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cond = NULL_RTX;
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op0 = &XEXP (src, 0);
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op1 = &XEXP (src, 1);
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}
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else
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return false;
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if (!REG_P (*op0) || !REG_P (*op1))
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return false;
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/* Swap the COMPARE arguments and its mask if there is a
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conflicting access in the previous insn. */
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prev_insn = PREV_INSN (insn);
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if (prev_insn != NULL_RTX && INSN_P (prev_insn)
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&& reg_referenced_p (*op1, PATTERN (prev_insn)))
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s390_swap_cmp (cond, op0, op1, insn);
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/* Check if there is a conflict with the next insn. If there
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was no conflict with the previous insn, then swap the
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COMPARE arguments and its mask. If we already swapped
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the operands, or if swapping them would cause a conflict
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with the previous insn, issue a NOP after the COMPARE in
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order to separate the two instuctions. */
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next_insn = NEXT_INSN (insn);
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if (next_insn != NULL_RTX && INSN_P (next_insn)
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&& s390_non_addr_reg_read_p (*op1, next_insn))
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{
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if (prev_insn != NULL_RTX && INSN_P (prev_insn)
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&& s390_non_addr_reg_read_p (*op0, prev_insn))
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{
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{
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/* Handle compare and branch and branch on count
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if (REGNO (*op1) == 0)
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instructions. */
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emit_insn_after (gen_nop1 (), insn);
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rtx pattern = single_set (insn);
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else
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emit_insn_after (gen_nop (), insn);
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if (!pattern
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insn_added_p = true;
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|| SET_DEST (pattern) != pc_rtx
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|| GET_CODE (SET_SRC (pattern)) != IF_THEN_ELSE)
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continue;
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cond = XEXP (SET_SRC (pattern), 0);
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op0 = &XEXP (cond, 0);
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op1 = &XEXP (cond, 1);
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}
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else if (GET_CODE (PATTERN (insn)) == SET)
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{
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rtx src, dest;
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/* Handle normal compare instructions. */
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src = SET_SRC (PATTERN (insn));
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dest = SET_DEST (PATTERN (insn));
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if (!REG_P (dest)
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|| !CC_REGNO_P (REGNO (dest))
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|| GET_CODE (src) != COMPARE)
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continue;
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/* s390_swap_cmp will try to find the conditional
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jump when passing NULL_RTX as condition. */
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cond = NULL_RTX;
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op0 = &XEXP (src, 0);
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op1 = &XEXP (src, 1);
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}
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}
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else
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else
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continue;
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if (!REG_P (*op0) || !REG_P (*op1))
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continue;
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/* Swap the COMPARE arguments and its mask if there is a
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conflicting access in the previous insn. */
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prev_insn = PREV_INSN (insn);
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if (prev_insn != NULL_RTX && INSN_P (prev_insn)
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&& reg_referenced_p (*op1, PATTERN (prev_insn)))
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s390_swap_cmp (cond, op0, op1, insn);
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s390_swap_cmp (cond, op0, op1, insn);
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/* Check if there is a conflict with the next insn. If there
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was no conflict with the previous insn, then swap the
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COMPARE arguments and its mask. If we already swapped
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the operands, or if swapping them would cause a conflict
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with the previous insn, issue a NOP after the COMPARE in
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order to separate the two instuctions. */
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next_insn = NEXT_INSN (insn);
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if (next_insn != NULL_RTX && INSN_P (next_insn)
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&& s390_non_addr_reg_read_p (*op1, next_insn))
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{
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if (prev_insn != NULL_RTX && INSN_P (prev_insn)
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&& s390_non_addr_reg_read_p (*op0, prev_insn))
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{
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if (REGNO (*op1) == 0)
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emit_insn_after (gen_nop1 (), insn);
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else
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emit_insn_after (gen_nop (), insn);
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added_NOPs = 1;
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}
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else
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s390_swap_cmp (cond, op0, op1, insn);
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}
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}
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}
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return insn_added_p;
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/* Adjust branches if we added new instructions. */
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if (added_NOPs)
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shorten_branches (get_insns ());
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}
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}
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/* Perform machine-dependent processing. */
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/* Perform machine-dependent processing. */
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static void
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static void
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@ -9944,10 +9998,33 @@ s390_reorg (void)
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/* Try to optimize prologue and epilogue further. */
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/* Try to optimize prologue and epilogue further. */
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s390_optimize_prologue ();
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s390_optimize_prologue ();
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/* Eliminate z10-specific pipeline recycles related to some compare
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/* Walk over the insns and do some z10 specific changes. */
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instructions. */
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if (s390_tune == PROCESSOR_2097_Z10)
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if (s390_tune == PROCESSOR_2097_Z10)
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s390_z10_optimize_cmp ();
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{
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rtx insn;
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bool insn_added_p = false;
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/* The insn lengths and addresses have to be up to date for the
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following manipulations. */
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shorten_branches (get_insns ());
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for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
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{
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if (!INSN_P (insn) || INSN_CODE (insn) <= 0)
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continue;
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if (JUMP_P (insn))
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insn_added_p |= s390_z10_fix_long_loop_prediction (insn);
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if (GET_CODE (PATTERN (insn)) == PARALLEL
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|| GET_CODE (PATTERN (insn)) == SET)
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insn_added_p |= s390_z10_optimize_cmp (insn);
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}
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/* Adjust branches if we added new instructions. */
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if (insn_added_p)
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shorten_branches (get_insns ());
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}
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}
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}
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@ -1046,6 +1046,64 @@
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(const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
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(const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
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; 10 byte for clgr/jg
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; 10 byte for clgr/jg
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; And now the same two patterns as above but with a negated CC mask.
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; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr
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; The following instructions do a complementary access of their second
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; operand (z01 only): crj_c, cgrjc, cr, cgr
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(define_insn "*icmp_and_br_signed_<mode>"
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[(set (pc)
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(if_then_else (match_operator 0 "s390_signed_integer_comparison"
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[(match_operand:GPR 1 "register_operand" "d,d")
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(match_operand:GPR 2 "nonmemory_operand" "d,C")])
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(pc)
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(label_ref (match_operand 3 "" ""))))
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(clobber (reg:CC CC_REGNUM))]
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"TARGET_Z10"
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{
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if (get_attr_length (insn) == 6)
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return which_alternative ?
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"c<g>ij%D0\t%1,%c2,%l3" : "c<g>rj%D0\t%1,%2,%l3";
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else
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return which_alternative ?
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"c<g>fi\t%1,%c2\;jg%D0\t%l3" : "c<g>r\t%1,%2\;jg%D0\t%l3";
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}
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[(set_attr "op_type" "RIE")
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(set_attr "type" "branch")
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(set_attr "z10prop" "z10_super_c,z10_super")
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(set (attr "length")
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(if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
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(const_int 6) (const_int 12)))]) ; 8 byte for cr/jg
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; 10 byte for cgr/jg
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; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr
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; The following instructions do a complementary access of their second
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; operand (z10 only): clrj, clgrj, clr, clgr
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(define_insn "*icmp_and_br_unsigned_<mode>"
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[(set (pc)
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(if_then_else (match_operator 0 "s390_unsigned_integer_comparison"
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[(match_operand:GPR 1 "register_operand" "d,d")
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||||||
|
(match_operand:GPR 2 "nonmemory_operand" "d,I")])
|
||||||
|
(pc)
|
||||||
|
(label_ref (match_operand 3 "" ""))))
|
||||||
|
(clobber (reg:CC CC_REGNUM))]
|
||||||
|
"TARGET_Z10"
|
||||||
|
{
|
||||||
|
if (get_attr_length (insn) == 6)
|
||||||
|
return which_alternative ?
|
||||||
|
"cl<g>ij%D0\t%1,%b2,%l3" : "cl<g>rj%D0\t%1,%2,%l3";
|
||||||
|
else
|
||||||
|
return which_alternative ?
|
||||||
|
"cl<g>fi\t%1,%b2\;jg%D0\t%l3" : "cl<g>r\t%1,%2\;jg%D0\t%l3";
|
||||||
|
}
|
||||||
|
[(set_attr "op_type" "RIE")
|
||||||
|
(set_attr "type" "branch")
|
||||||
|
(set_attr "z10prop" "z10_super_c,z10_super")
|
||||||
|
(set (attr "length")
|
||||||
|
(if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000))
|
||||||
|
(const_int 6) (const_int 12)))]) ; 8 byte for clr/jg
|
||||||
|
; 10 byte for clgr/jg
|
||||||
|
|
||||||
;;
|
;;
|
||||||
;;- Move instructions.
|
;;- Move instructions.
|
||||||
;;
|
;;
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue