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Fix 16-bit floating point vector ordering. 

2025-10-17  Michael Meissner  <meissner@linux.ibm.com>

gcc/

	* config/rs6000/float16.cd (fp16_vectorization): Fix 16-bit floating
	point ordering.
This commit is contained in:
Michael Meissner 2025-10-17 11:53:02 -04:00
parent f69be51e46
commit c6f7231367
1 changed files with 11 additions and 4 deletions
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15
gcc/config/rs6000/float16.cc
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@ -247,16 +247,23 @@ fp16_vectorization (enum rtx_code icode,
op_hi[i] = gen_reg_rtx (V4SFmode); /* high register. */
op_lo[i] = gen_reg_rtx (V4SFmode); /* low register. */
rtx interleave_hi = gen_reg_rtx (result_mode);
rtx interleave_lo = gen_reg_rtx (result_mode);
rtx orig = op_orig[i];
rs6000_expand_interleave (interleave_hi, orig, orig, !BYTES_BIG_ENDIAN);
rs6000_expand_interleave (interleave_lo, orig, orig, BYTES_BIG_ENDIAN);
if (result_mode == V8HFmode)
{
emit_insn (gen_vec_unpacks_hi_v8hf (op_hi[i], op_orig[i]));
emit_insn (gen_vec_unpacks_lo_v8hf (op_lo[i], op_orig[i]));
emit_insn (gen_xvcvhpsp_v8hf (op_hi[i], interleave_hi));
emit_insn (gen_xvcvhpsp_v8hf (op_lo[i], interleave_lo));
}
else if (result_mode == V8BFmode)
{
emit_insn (gen_vec_unpacks_hi_v8bf (op_hi[i], op_orig[i]));
emit_insn (gen_vec_unpacks_lo_v8bf (op_lo[i], op_orig[i]));
emit_insn (gen_xvcvbf16spn_v8bf (op_hi[i], interleave_hi));
emit_insn (gen_xvcvbf16spn_v8bf (op_lo[i], interleave_lo));
}
else