The introduction of the empty __pair_base base class for PR 86751
changed the layout of std::pair<std::pair<...>, ...>. The outer pair and
its first member both have a base class of the same type, which cannot
exist at the same address. This causes the first member to be at a
non-zero offset.
The solution is to make the base class depend on the template
parameters, so that each pair type has a different base class type,
which allows the base classes of the outer pair and its first member to
have the same address.
PR libstdc++/87822
* include/bits/stl_pair.h (__pair_base): Change to class template.
(pair): Make base class type depend on template parameters.
* testsuite/20_util/pair/87822.cc: New test.
From-SVN: r265678
2018-10-31 Richard Biener <rguenther@suse.de>
PR middle-end/70359
PR middle-end/86270
* tree-outof-ssa.c (insert_backedge_copies): Restrict
copy generation to useful cases. Place the copy before
the definition of the backedge value when possible.
* gcc.target/i386/pr70359.c: New testcase.
* gcc.target/i386/pr86270.c: Likewise.
From-SVN: r265677
Handle store cacheline hazard for A700 cpus by inserting two NOP_S
between ST ST LD or their logical equivalent (like ST ST NOP_S NOP_S
J_L.D LD)
gcc/
xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com>
* config/arc/arc-arch.h (ARC_TUNE_ARC7XX): New tune value.
* config/arc/arc.c (arc_active_insn): New function.
(check_store_cacheline_hazard): Likewise.
(workaround_arc_anomaly): Use check_store_cacheline_hazard.
(arc_override_options): Disable delay slot scheduler for older
A7.
(arc_store_addr_hazard_p): New implementation, old one renamed to
...
(arc_store_addr_hazard_internal_p): Renamed.
(arc_reorg): Don't combine into brcc instructions which are part
of hardware hazard solution.
* config/arc/arc.md (attr tune): Consider new arc7xx tune value.
(tune_arc700): Likewise.
* config/arc/arc.opt (arc7xx): New tune value.
* config/arc/arc700.md: Improve A7 scheduler.
From-SVN: r265676
2018-10-31 Martin Liska <mliska@suse.cz>
* config.h.in: Regenerate.
* configure: Likewise.
* sanitizer_common/Makefile.am: Include new files, remove old
files.
* sanitizer_common/Makefile.in: Regenerate.
* ubsan/Makefile.am: Include new files, remove old
files.
* ubsan/Makefile.in: Likewise.
* asan/Makefile.am: Include new files.
* asan/Makefile.in: Regenerate.
From-SVN: r265666
GCC ICEs under -mslow-flash-data and -mword-relocations because there
is no way to load an address, both literal pools and MOVW/MOVT being
forbidden. This patch gives an error message when both options are
specified by the user and adds the according dg-skip-if directives for
tests that use either of these options. It also explicitely set the
option when in PIC mode as per documentation rather than always check
for target_word_relocation together with flag_pic.
2018-10-31 Thomas Preud'homme <thomas.preudhomme@linaro.org>
gcc/
PR target/87374
* config/arm/arm.c (arm_option_check_internal): Disable the combined
use of -mslow-flash-data and -mword-relocations.
(arm_option_override): Enable -mword-relocations if -fpic or -fPIC.
* config/arm/arm.md (SYMBOL_REF MOVT splitter): Stop checking for
flag_pic.
* doc/invoke.texi (-mword-relocations): Mention conflict with
-mslow-flash-data.
(-mslow-flash-data): Reciprocally.
gcc/testsuite/
PR target/87374
* gcc.target/arm/movdi_movt.c: Skip if both -mslow-flash-data and
-mword-relocations would be passed when compiling the test.
* gcc.target/arm/movsi_movt.c: Likewise.
* gcc.target/arm/pr81863.c: Likewise.
* gcc.target/arm/thumb2-slow-flash-data-1.c: Likewise.
* gcc.target/arm/thumb2-slow-flash-data-2.c: Likewise.
* gcc.target/arm/thumb2-slow-flash-data-3.c: Likewise.
* gcc.target/arm/thumb2-slow-flash-data-4.c: Likewise.
* gcc.target/arm/thumb2-slow-flash-data-5.c: Likewise.
* gcc.target/arm/tls-disable-literal-pool.c: Likewise.
From-SVN: r265662
The LSE CASP instruction requires values to be placed in even
register pairs. A solution involving two additional register
classes was rejected in favor of the much simpler solution of
simply requiring all TImode values to be aligned.
* config/aarch64/aarch64.c (aarch64_hard_regno_mode_ok): Force
16-byte modes held in GP registers to use an even regno.
From-SVN: r265661
Fix constraints; avoid unnecessary split. Drop the use of the atomic_op
iterator in favor of the ATOMIC_LDOP iterator; this is simplier and more
logical for ldclr aka bic.
* config/aarch64/aarch64.c (aarch64_emit_bic): Remove.
(aarch64_atomic_ldop_supported_p): Remove.
(aarch64_gen_atomic_ldop): Remove.
* config/aarch64/atomic.md (atomic_<atomic_optab><ALLI>):
Fully expand LSE operations here.
(atomic_fetch_<atomic_optab><ALLI>): Likewise.
(atomic_<atomic_optab>_fetch<ALLI>): Likewise.
(aarch64_atomic_<ATOMIC_LDOP><ALLI>_lse): Drop atomic_op iterator
and use ATOMIC_LDOP instead; use register_operand for the input;
drop the split and emit insns directly.
(aarch64_atomic_fetch_<ATOMIC_LDOP><ALLI>_lse): Likewise.
(aarch64_atomic_<atomic_op>_fetch<ALLI>_lse): Remove.
(@aarch64_atomic_load<ATOMIC_LDOP><ALLI>): Remove.
From-SVN: r265660
Allow zero as an input; fix constraints; avoid unnecessary split.
* config/aarch64/aarch64.c (aarch64_emit_atomic_swap): Remove.
(aarch64_gen_atomic_ldop): Don't call it.
* config/aarch64/atomics.md (atomic_exchange<ALLI>):
Use aarch64_reg_or_zero.
(aarch64_atomic_exchange<ALLI>): Likewise.
(aarch64_atomic_exchange<ALLI>_lse): Remove split; remove & from
operand 0; use aarch64_reg_or_zero for input; merge ...
(@aarch64_atomic_swp<ALLI>): ... this and remove.
From-SVN: r265659
ChangeLog:
2018-10-31 Iain Buclaw <ibuclaw@gdcproject.org>
PR bootstrap/87788
PR d/87799
* configure: Rebuild.
* configure.ac: Disable D on systems where it is known not to work.
libphobos/ChangeLog:
2018-10-31 Iain Buclaw <ibuclaw@gdcproject.org>
PR bootstrap/87789
PR d/87818
PR d/87819
* configure.tgt: New file.
From-SVN: r265658
Do not zero-extend the input to the cas for subword operations;
instead, use the appropriate zero-extending compare insns.
Correct the predicates and constraints for immediate expected operand.
* config/aarch64/aarch64.c (aarch64_gen_compare_reg_maybe_ze): New.
(aarch64_split_compare_and_swap): Use it.
(aarch64_expand_compare_and_swap): Likewise. Remove convert_modes;
test oldval against the proper predicate.
* config/aarch64/atomics.md (@atomic_compare_and_swap<ALLI>):
Use nonmemory_operand for expected.
(cas_short_expected_pred): New.
(@aarch64_compare_and_swap<SHORT>): Use it; use "rn" not "rI" to match.
(@aarch64_compare_and_swap<GPI>): Use "rn" not "rI" for expected.
* config/aarch64/predicates.md (aarch64_plushi_immediate): New.
(aarch64_plushi_operand): New.
From-SVN: r265657
The cas insn is a single insn, and if expanded properly need not
be split after reload. Use the proper inputs for the insn.
* config/aarch64/aarch64.c (aarch64_expand_compare_and_swap):
Force oldval into the rval register for TARGET_LSE; emit the compare
during initial expansion so that it may be deleted if unused.
(aarch64_gen_atomic_cas): Remove.
* config/aarch64/atomics.md (@aarch64_compare_and_swap<SHORT>_lse):
Change =&r to +r for operand 0; use match_dup for operand 2;
remove is_weak and mod_f operands as unused. Drop the split
and merge with...
(@aarch64_atomic_cas<SHORT>): ... this pattern's output; remove.
(@aarch64_compare_and_swap<GPI>_lse): Similarly.
(@aarch64_atomic_cas<GPI>): Similarly.
From-SVN: r265656
2018-10-30 Thomas Koenig <tkoenig@gcc.gnu.org>
PR fortran/85896
* simplify.c (simplify_min_max): Do not convert the type of the
return expression.
2018-10-30 Thomas Koenig <tkoenig@gcc.gnu.org>
PR fortran/85896
* gfortran.dg/min_max_type.f90: New test.
From-SVN: r265649
After r265398, the ira-shrinkwrap-prep-[12].c tests fail on all
targets, because the IRA feature tested can only move hard registers
down, and we no longer have hard registers for the function parameters
at this stage.
gcc/testsuite/
PR rtl-optimization/87708
gcc.dg/ira-shrinkwrap-prep-1.c: xfail test.
gcc.dg/ira-shrinkwrap-prep-2.c: xfail test.
From-SVN: r265639
(free_lang_data_d, add_tree_to_fld_list, fld_worklist_push): Move
head in file.
(free_lang_data_in_type): Forward declare.
(fld_type_variant_equal_p): New function.
(fld_type_variant): New function
(fld_incomplete_types): New hash.
(fld_incomplete_type_of): New function
(fld_simplfied-type): New function.
(free_lang_data_in_decl): Add fld parameter; simplify type of FIELD_DECL
(free_lang_data): Allocate and free fld_incomplete_type; update call
of free_lang_data_in_decl.
From-SVN: r265638
2018-10-30 Aaron Sawdey <acsawdey@linux.ibm.com>
* config/rs6000/rs6000.md (bswapdi2): Force address into register
if not in indexed or indirect form.
(bswapdi2_load): Change predicate to indexed_or_indirect_operand.
(bswapdi2_store): Ditto.
* config/rs6000/rs6000.c (rs6000_force_indexed_or_indirect_mem): New
helper function.
* config/rs6000/rs6000-protos.h (rs6000_force_indexed_or_indirect_mem):
Prototype for helper function.
From-SVN: r265632
If the allocator isn't default constructible then checking if the
default constructor throws in an exception specification makes the
declaration invalid. Use the type trait instead.
PR libstdc++/87809
* include/bits/forward_list.h (_Fwd_list_impl::_Fwd_list_impl()): Use
trait in exception-specification instead of possibly invalid
expression.
* include/bits/stl_bvector.h (_Bvector_impl::_Bvector_impl()):
Likewise.
* include/bits/stl_list.h (_List_impl::_List_impl()): Likewise.
* include/bits/stl_vector.h (_Vector_impl::_Vector_impl()): Likewise.
* testsuite/23_containers/forward_list/cons/87809.cc: New test.
* testsuite/23_containers/list/cons/87809.cc: New test.
* testsuite/23_containers/vector/bool/cons/87809.cc: New test.
* testsuite/23_containers/vector/cons/87809.cc: New test.
From-SVN: r265626
Previously the _M_Nb member was incremented before calling
_M_unchecked_set which meant that the bit being set was out of bounds.
It either set the wrong bit in an allocated word, or accessed beyond the
end of the allocated memory in the _M_w vector. The fix for the bug is
to update the _M_Nb member after using it as an index.
As an optimisation, when a new block needs to be appended the call to
_M_unchecked_set can be avoided by appending a block with the least
significant bit already set to the desired value.
PR libstdc++/87784
* include/tr2/dynamic_bitset (dynamic_bitset::push_back): When there
are no unused bits in the last block, append a new block with the
right value so the bit doesn't need to be set. Only increment size
after setting the new bit, not before.
* testsuite/tr2/dynamic_bitset/pr87784.cc: New test.
From-SVN: r265625
2018-10-30 Michael Ploujnikov <michael.ploujnikov@oracle.com>
* cgraph.h (clone_function_name_1): Replaced by new
clone_function_name_numbered that takes name as string; for
privatize_symbol_name_1 use only.
(clone_function_name): Renamed to
clone_function_name_numbered to be explicit about numbering.
(clone_function_name): New two-argument function that does
not number its output.
(clone_function_name): New three-argument function that
takes a number to append to its output.
* cgraphclones.c (duplicate_thunk_for_node):
(clone_function_name_1): Renamed.
(clone_function_name_numbered): Two new functions.
(clone_function_name): Improved documentation.
(cgraph_node::create_virtual_clone): Use clone_function_name_numbered.
* config/rs6000/rs6000.c (make_resolver_func): Ditto.
* final.c (final_scan_insn_1): Use the new clone_function_name
without numbering.
* multiple_target.c (create_dispatcher_calls): Ditto.
(create_target_clone): Ditto.
* omp-expand.c (grid_expand_target_grid_body): Ditto.
* omp-low.c (create_omp_child_function_name): Ditto.
* omp-simd-clone.c (simd_clone_create): Ditto.
* symtab.c (simd_symtab_node::noninterposable_alias): Use the
new clone_function_name without numbering.
2018-10-30 Michael Ploujnikov <michael.ploujnikov@oracle.com>
* lto-partition.c (privatize_symbol_name_1): Use
clone_function_name_numbered.
2018-10-30 Michael Ploujnikov <michael.ploujnikov@oracle.com>
* gcc.dg/tree-prof/cold_partition_label.c: Update for cold
section names without numbers.
* gcc.dg/tree-prof/section-attr-1.c: Ditto.
* gcc.dg/tree-prof/section-attr-2.c: Ditto.
* gcc.dg/tree-prof/section-attr-3.c: Ditto.
From-SVN: r265621
PR bootstrap/87747 would have been significantly easier to track down if
the pool allocator had faulted an attempt to configure it to allocate
zero-sized objects. Instead, this slipped through and we later hit
memory corruption when the assumed size turned out to be different to
the configured size.
While, theoretically, there might be a use case for this, it seems
unlikely to me that GCC would have such a use. So this patch adds a
checking assert that the object size is not zero.
* alloc-pool.h (base_pool_allocator <TBlockAllocator>::initialize):
Assert that the allocation size is not zero.
From-SVN: r265620
Just as one needs run-time initialization of mutexes, one needs to
destroy them properly to allow the OS to release resources associated
with the semaphore.
From-SVN: r265616
PR c++/87721 reports a crash in get_substring_ranges_for_loc introduced
by r265271, my fix for PR 87562.
The new issue occurs when attempting to get a location with a string
literal inside a macro in which the first token is __FILE__ (formed via
concatenation). Attempting to get the spelling location of __FILE__
fails, leading to NULL for start_ord_map and final_ord_map, and thus
a NULL pointer dereference.
Given that our "on-demand" substring locations approach reparses the
string literals, there isn't a good way to access the locations inside
such string literals: attempting to reparse __FILE__ fails with a
"missing open quote".
This patch applies the easy fix by gracefully rejecting the case where
the spelling locations for the start or finish give us NULL maps.
gcc/ChangeLog:
PR c++/87721
* input.c (get_substring_ranges_for_loc): Detect if
linemap_resolve_location gives us a NULL map, and reject
this case.
gcc/testsuite/ChangeLog:
PR c++/87721
* c-c++-common/substring-location-PR-87721.c: New test.
* gcc.dg/plugin/diagnostic-test-string-literals-1.c: Add test for
PR 87721.
* gcc.dg/plugin/diagnostic_plugin_test_string_literals.c
(test_string_literals): Fold the index arguments before checking
for INTEGER_CST.
From-SVN: r265611
Jonathan Wakely