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5 Commits
d23196f0d3 ... f69be51e46

Author SHA1 Message Date
Michael Meissner f69be51e46 Revert changes 2025-10-17 04:23:33 -04:00
Michael Meissner 3967387d94 Update ChangeLog.* 2025-10-17 03:51:20 -04:00
Michael Meissner 7b0c41ca37 Fix 16-bit floating point ordering. 
2025-10-17  Michael Meissner  <meissner@linux.ibm.com>

gcc/

	* config/rs6000/ffloat16.md (vec_unpacks_hi_v8hf): Fix ordering issue.
	(vec_unpacks_lo_v8hf): Likewise.
	(vec_unpacks_hi_v8bf): Likewise.
	(vec_unpacks_lo_v8bf): Likewise.
 2025-10-17 03:49:39 -04:00
Michael Meissner 357d0be634 Update ChangeLog.* 2025-10-17 02:08:35 -04:00
Michael Meissner 1303873a51 Fix typo in vectorizing __bfloat16. 
2025-10-17  Michael Meissner  <meissner@linux.ibm.com>

gcc/

	* config/rs6000/float16.cc (fp16_vectorization):  Fix typo in
	vectorizing __bfloat16.
	* config/rs6000/float16.md (xvcvhpsp_v8hf): Fix comment.
 2025-10-17 02:07:45 -04:00
3 changed files with 17 additions and 3 deletions
Show Stats Expand all files Collapse all files

14
gcc/ChangeLog.float
View File

@ -1,3 +1,17 @@
==================== Branch work222-float, patch #337 was reverted ====================
==================== Branch work222-float, patch #336 ====================
Fix typo in vectorizing __bfloat16.
2025-10-17 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/float16.cc (fp16_vectorization): Fix typo in
vectorizing __bfloat16.
* config/rs6000/float16.md (xvcvhpsp_v8hf): Fix comment.
==================== Branch work222-float, patch #335 ====================
Add vectorized 16-bit floating point binary operation support.

4
gcc/config/rs6000/float16.cc
View File

@ -255,8 +255,8 @@ fp16_vectorization (enum rtx_code icode,
else if (result_mode == V8BFmode)
{
emit_insn (gen_vec_unpacks_hi_v8hf (op_hi[i], op_orig[i]));
emit_insn (gen_vec_unpacks_lo_v8hf (op_lo[i], op_orig[i]));
emit_insn (gen_vec_unpacks_hi_v8bf (op_hi[i], op_orig[i]));
emit_insn (gen_vec_unpacks_lo_v8bf (op_lo[i], op_orig[i]));
}
else

2
gcc/config/rs6000/float16.md
View File

@ -1030,7 +1030,7 @@
DONE;
})
;; Used for vector conversion from __bfloat16
;; Used for vector conversion from _Float16
(define_insn "xvcvhpsp_v8hf"
[(set (match_operand:V4SF 0 "vsx_register_operand" "=wa")
(unspec:V4SF [(match_operand:V8HF 1 "vsx_register_operand" "wa")]