Ramana Radhakrishnan 23fa65d6f3 re PR target/66200 (GCC for ARM / AArch64 doesn't define TARGET_RELAXED_ORDERING) ... Fix PR target/66200 This applies the same fix for PR target/66200 for AArch64 on the GCC 5 branch as on the 4.9 branch. On trunk we've fixed this differently by optimizing the access to the guard variable using a load acquire style instruction. 2015-06-24 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> PR target/66200 * g++.dg/abi/aarch64_guard1.C: Adjust. 2015-06-24 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> PR target/66200 * configure.host (host_cpu): Add aarch64 case. * config/cpu/aarch64/atomic_word.h: New file. From-SVN: r224890		2015-06-24 09:59:28 +00:00
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aarch64	re PR target/66200 (GCC for ARM / AArch64 doesn't define TARGET_RELAXED_ORDERING)	2015-06-24 09:59:28 +00:00
alpha	Update copyright years.	2015-01-05 13:33:28 +01:00
arm	Update copyright years.	2015-01-05 13:33:28 +01:00
cris	Update copyright years.	2015-01-05 13:33:28 +01:00
generic	Update copyright years.	2015-01-05 13:33:28 +01:00
hppa	Update copyright years.	2015-01-05 13:33:28 +01:00
i386	Update copyright years.	2015-01-05 13:33:28 +01:00
i486	Update copyright years.	2015-01-05 13:33:28 +01:00
ia64	Update copyright years.	2015-01-05 13:33:28 +01:00
m68k	Update copyright years.	2015-01-05 13:33:28 +01:00
microblaze	Update copyright years.	2015-01-05 13:33:28 +01:00
powerpc	re PR target/66224 (PowerPC _GLIBCXX_READ_MEM_BARRIER too weak)	2015-05-22 08:43:02 -04:00
sh	re PR libstdc++/29366 (atomics config for sh is weird)	2015-01-25 16:54:33 +00:00
sparc	Update copyright years.	2015-01-05 13:33:28 +01:00