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dt-bindings: mtd: davinci: convert to yaml
Convert the bindings to yaml format. Signed-off-by: Marcus Folkesson <marcus.folkesson@gmail.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
This commit is contained in:
Marcus Folkesson
committed by
Miquel Raynal
Miquel Raynal
parent
40384c840e
commit
e0a4f50fce
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Device tree bindings for Texas instruments Davinci/Keystone NAND controller
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This file provides information, what the device node for the davinci/keystone
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NAND interface contains.
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Documentation:
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Davinci DM646x - https://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf
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Kestone - https://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf
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Required properties:
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- compatible: "ti,davinci-nand"
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"ti,keystone-nand"
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- reg: Contains 2 offset/length values:
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- offset and length for the access window.
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- offset and length for accessing the AEMIF
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control registers.
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- ti,davinci-chipselect: number of chipselect. Indicates on the
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davinci_nand driver which chipselect is used
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for accessing the nand.
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Can be in the range [0-3].
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Recommended properties :
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- ti,davinci-mask-ale: mask for ALE. Needed for executing address
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phase. These offset will be added to the base
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address for the chip select space the NAND Flash
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device is connected to.
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If not set equal to 0x08.
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- ti,davinci-mask-cle: mask for CLE. Needed for executing command
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phase. These offset will be added to the base
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address for the chip select space the NAND Flash
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device is connected to.
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If not set equal to 0x10.
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- ti,davinci-mask-chipsel: mask for chipselect address. Needed to mask
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addresses for given chipselect.
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- nand-ecc-mode: operation mode of the NAND ecc mode. ECC mode
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valid values for davinci driver:
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- "none"
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- "soft"
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- "hw"
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- ti,davinci-ecc-bits: used ECC bits, currently supported 1 or 4.
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- nand-bus-width: buswidth 8 or 16. If not present 8.
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- nand-on-flash-bbt: use flash based bad block table support. OOB
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identifier is saved in OOB area. If not present
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false.
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Deprecated properties:
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- ti,davinci-ecc-mode: operation mode of the NAND ecc mode. ECC mode
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valid values for davinci driver:
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- "none"
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- "soft"
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- "hw"
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- ti,davinci-nand-buswidth: buswidth 8 or 16. If not present 8.
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- ti,davinci-nand-use-bbt: use flash based bad block table support. OOB
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identifier is saved in OOB area. If not present
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false.
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Nand device bindings may contain additional sub-nodes describing partitions of
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the address space. See mtd.yaml for more detail. The NAND Flash timing
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values must be programmed in the chip select’s node of AEMIF
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memory-controller (see Documentation/devicetree/bindings/memory-controllers/
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davinci-aemif.txt).
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Example(da850 EVM ):
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nand_cs3@62000000 {
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compatible = "ti,davinci-nand";
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reg = <0x62000000 0x807ff
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0x68000000 0x8000>;
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ti,davinci-chipselect = <1>;
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ti,davinci-mask-ale = <0>;
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ti,davinci-mask-cle = <0>;
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ti,davinci-mask-chipsel = <0>;
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nand-ecc-mode = "hw";
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ti,davinci-ecc-bits = <4>;
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nand-on-flash-bbt;
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partition@180000 {
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label = "ubifs";
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reg = <0x180000 0x7e80000>;
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};
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};
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124
Documentation/devicetree/bindings/mtd/ti,davinci-nand.yaml
Normal file
124
Documentation/devicetree/bindings/mtd/ti,davinci-nand.yaml
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@@ -0,0 +1,124 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/mtd/ti,davinci-nand.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: TI DaVinci NAND controller
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maintainers:
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- Marcus Folkesson <marcus.folkesson@gmail.com>
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allOf:
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- $ref: nand-controller.yaml
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properties:
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compatible:
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enum:
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- ti,davinci-nand
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- ti,keystone-nand
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reg:
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items:
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- description: Access window.
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- description: AEMIF control registers.
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partitions:
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$ref: /schemas/mtd/partitions/partitions.yaml
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ti,davinci-chipselect:
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description:
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Number of chipselect. Indicate on the davinci_nand driver which
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chipselect is used for accessing the nand.
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [0, 1, 2, 3]
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ti,davinci-mask-ale:
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description:
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Mask for ALE. Needed for executing address phase. These offset will be
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added to the base address for the chip select space the NAND Flash
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device is connected to.
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$ref: /schemas/types.yaml#/definitions/uint32
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default: 0x08
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ti,davinci-mask-cle:
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description:
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Mask for CLE. Needed for executing command phase. These offset will be
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added to the base address for the chip select space the NAND Flash device
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is connected to.
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$ref: /schemas/types.yaml#/definitions/uint32
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default: 0x10
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ti,davinci-mask-chipsel:
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description:
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Mask for chipselect address. Needed to mask addresses for given
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chipselect.
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$ref: /schemas/types.yaml#/definitions/uint32
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default: 0
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ti,davinci-ecc-bits:
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description: Used ECC bits.
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enum: [1, 4]
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ti,davinci-ecc-mode:
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description: Operation mode of the NAND ECC mode.
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$ref: /schemas/types.yaml#/definitions/string
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enum: [none, soft, hw, on-die]
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deprecated: true
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ti,davinci-nand-buswidth:
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description: Bus width to the NAND chip.
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [8, 16]
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default: 8
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deprecated: true
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ti,davinci-nand-use-bbt:
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type: boolean
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description:
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Use flash based bad block table support. OOB identifier is saved in OOB
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area.
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deprecated: true
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required:
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- compatible
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- reg
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- ti,davinci-chipselect
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unevaluatedProperties: false
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examples:
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- |
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bus {
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#address-cells = <2>;
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#size-cells = <1>;
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nand-controller@2000000,0 {
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compatible = "ti,davinci-nand";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0 0x02000000 0x02000000>,
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<1 0x00000000 0x00008000>;
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ti,davinci-chipselect = <1>;
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ti,davinci-mask-ale = <0>;
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ti,davinci-mask-cle = <0>;
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ti,davinci-mask-chipsel = <0>;
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ti,davinci-nand-buswidth = <16>;
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ti,davinci-ecc-mode = "hw";
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ti,davinci-ecc-bits = <4>;
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ti,davinci-nand-use-bbt;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "u-boot env";
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reg = <0 0x020000>;
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};
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};
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};
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};
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