Victor Zhao 672c0218e3 drm/amdgpu: add mode2 reset for sienna_cichlid ...

To meet the requirement for multi container usecase which needs
a quicker reset and not causing VRAM lost, adding the Mode2
reset handler for sienna_cichlid.

v2: move skip mode2 flag part separately

v3: remove the use of asic_reset_res

Signed-off-by: Victor Zhao <Victor.Zhao@amd.com>
Acked-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

2022-08-16 18:14:31 -04:00

1.3 KiB

Raw Blame History

View Raw