Commit 00c6f39c authored by Anup Patel's avatar Anup Patel Committed by Anup Patel
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dt-bindings: riscv: Add Zicond extension entry 



Add an entry for the Zicond extension to the riscv,isa-extensions property.

Signed-off-by: default avatarAnup Patel <apatel@ventanamicro.com>
Reviewed-by: default avatarAndrew Jones <ajones@ventanamicro.com>
Reviewed-by: default avatarConor Dooley <conor.dooley@microchip.com>
Signed-off-by: default avatarAnup Patel <anup@brainfault.org>
parent 662a601a

Documentation/devicetree/bindings/riscv/extensions.yaml

+6 −0
Original line number Diff line number Diff line
@@ -218,6 +218,12 @@ properties: 
            ratified in the 20191213 version of the unprivileged ISA

            specification.



        - const: zicond

          description:

            The standard Zicond extension for conditional arithmetic and

            conditional-select/move operations as ratified in commit 95cf1f9

            ("Add changes requested by Ved during signoff") of riscv-zicond.



        - const: zicsr

          description: |

            The standard Zicsr extension for control and status register