Commit 01abac26 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'perf-tools-fixes-for-v6.13-2024-12-12' of...

Merge tag 'perf-tools-fixes-for-v6.13-2024-12-12' of git://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools

Pull perf tools fixes from Namhyung Kim:
 "A set of random fixes for this cycle.

  perf record:
   - Fix build-id event size calculation in perf record
   - Fix perf record -C/--cpu option on hybrid systems
   - Fix perf mem record with precise-ip on SapphireRapids

  perf test:
   - Refresh hwmon directory before reading the test files
   - Make sure system_tsc_freq event is tested on x86 only

  Others:
   - Usual header file sync
   - Fix undefined behavior in perf ftrace profile
   - Properly initialize a return variable in perf probe"

* tag 'perf-tools-fixes-for-v6.13-2024-12-12' of git://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools: (21 commits)
  perf probe: Fix uninitialized variable
  libperf: evlist: Fix --cpu argument on hybrid platform
  perf test expr: Fix system_tsc_freq for only x86
  perf test hwmon_pmu: Fix event file location
  perf hwmon_pmu: Use openat rather than dup to refresh directory
  perf ftrace: Fix undefined behavior in cmp_profile_data()
  perf tools: Fix precise_ip fallback logic
  perf tools: Fix build error on generated/fs_at_flags_array.c
  tools headers: Sync uapi/linux/prctl.h with the kernel sources
  tools headers: Sync uapi/linux/mount.h with the kernel sources
  tools headers: Sync uapi/linux/fcntl.h with the kernel sources
  tools headers: Sync uapi/asm-generic/mman.h with the kernel sources
  tools headers: Sync *xattrat syscall changes with the kernel sources
  tools headers: Sync arm64 kvm header with the kernel sources
  tools headers: Sync x86 kvm and cpufeature headers with the kernel
  tools headers: Sync uapi/linux/kvm.h with the kernel sources
  tools headers: Sync uapi/linux/perf_event.h with the kernel sources
  tools headers: Sync uapi/drm/drm.h with the kernel sources
  perf machine: Initialize machine->env to address a segfault
  perf test: Don't signal all processes on system when interrupting tests
  ...
parents eefa7a9c 434fffa9
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+6 −0
Original line number Diff line number Diff line
@@ -484,6 +484,12 @@ enum {
 */
#define KVM_SYSTEM_EVENT_RESET_FLAG_PSCI_RESET2	(1ULL << 0)

/*
 * Shutdown caused by a PSCI v1.3 SYSTEM_OFF2 call.
 * Valid only when the system event has a type of KVM_SYSTEM_EVENT_SHUTDOWN.
 */
#define KVM_SYSTEM_EVENT_SHUTDOWN_FLAG_PSCI_OFF2	(1ULL << 0)

/* run->fail_entry.hardware_entry_failure_reason codes. */
#define KVM_EXIT_FAIL_ENTRY_CPU_UNSUPPORTED	(1ULL << 0)

+9 −2
Original line number Diff line number Diff line
@@ -215,7 +215,7 @@
#define X86_FEATURE_SPEC_STORE_BYPASS_DISABLE	( 7*32+23) /* Disable Speculative Store Bypass. */
#define X86_FEATURE_LS_CFG_SSBD		( 7*32+24)  /* AMD SSBD implementation via LS_CFG MSR */
#define X86_FEATURE_IBRS		( 7*32+25) /* "ibrs" Indirect Branch Restricted Speculation */
#define X86_FEATURE_IBPB		( 7*32+26) /* "ibpb" Indirect Branch Prediction Barrier */
#define X86_FEATURE_IBPB		( 7*32+26) /* "ibpb" Indirect Branch Prediction Barrier without a guaranteed RSB flush */
#define X86_FEATURE_STIBP		( 7*32+27) /* "stibp" Single Thread Indirect Branch Predictors */
#define X86_FEATURE_ZEN			( 7*32+28) /* Generic flag for all Zen and newer */
#define X86_FEATURE_L1TF_PTEINV		( 7*32+29) /* L1TF workaround PTE inversion */
@@ -317,6 +317,9 @@
#define X86_FEATURE_ZEN1		(11*32+31) /* CPU based on Zen1 microarchitecture */

/* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
#define X86_FEATURE_SHA512		(12*32+ 0) /* SHA512 instructions */
#define X86_FEATURE_SM3			(12*32+ 1) /* SM3 instructions */
#define X86_FEATURE_SM4			(12*32+ 2) /* SM4 instructions */
#define X86_FEATURE_AVX_VNNI		(12*32+ 4) /* "avx_vnni" AVX VNNI instructions */
#define X86_FEATURE_AVX512_BF16		(12*32+ 5) /* "avx512_bf16" AVX512 BFLOAT16 instructions */
#define X86_FEATURE_CMPCCXADD           (12*32+ 7) /* CMPccXADD instructions */
@@ -348,6 +351,7 @@
#define X86_FEATURE_CPPC		(13*32+27) /* "cppc" Collaborative Processor Performance Control */
#define X86_FEATURE_AMD_PSFD            (13*32+28) /* Predictive Store Forwarding Disable */
#define X86_FEATURE_BTC_NO		(13*32+29) /* Not vulnerable to Branch Type Confusion */
#define X86_FEATURE_AMD_IBPB_RET	(13*32+30) /* IBPB clears return address predictor */
#define X86_FEATURE_BRS			(13*32+31) /* "brs" Branch Sampling available */

/* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */
@@ -472,7 +476,9 @@
#define X86_FEATURE_BHI_CTRL		(21*32+ 2) /* BHI_DIS_S HW control available */
#define X86_FEATURE_CLEAR_BHB_HW	(21*32+ 3) /* BHI_DIS_S HW control enabled */
#define X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT (21*32+ 4) /* Clear branch history at vmexit using SW loop */
#define X86_FEATURE_AMD_FAST_CPPC		(21*32 + 5) /* AMD Fast CPPC */
#define X86_FEATURE_AMD_FAST_CPPC	(21*32 + 5) /* Fast CPPC */
#define X86_FEATURE_AMD_HETEROGENEOUS_CORES (21*32 + 6) /* Heterogeneous Core Topology */
#define X86_FEATURE_AMD_WORKLOAD_CLASS	(21*32 + 7) /* Workload Classification */

/*
 * BUG word(s)
@@ -523,4 +529,5 @@
#define X86_BUG_DIV0			X86_BUG(1*32 + 1) /* "div0" AMD DIV0 speculation bug */
#define X86_BUG_RFDS			X86_BUG(1*32 + 2) /* "rfds" CPU is vulnerable to Register File Data Sampling */
#define X86_BUG_BHI			X86_BUG(1*32 + 3) /* "bhi" CPU is affected by Branch History Injection */
#define X86_BUG_IBPB_NO_RET	   	X86_BUG(1*32 + 4) /* "ibpb_no_ret" IBPB omits return target predictions */
#endif /* _ASM_X86_CPUFEATURES_H */
+1 −0
Original line number Diff line number Diff line
@@ -440,6 +440,7 @@ struct kvm_sync_regs {
#define KVM_X86_QUIRK_FIX_HYPERCALL_INSN	(1 << 5)
#define KVM_X86_QUIRK_MWAIT_NEVER_UD_FAULTS	(1 << 6)
#define KVM_X86_QUIRK_SLOT_ZAP_ALL		(1 << 7)
#define KVM_X86_QUIRK_STUFF_FEATURE_MSRS	(1 << 8)

#define KVM_STATE_NESTED_FORMAT_VMX	0
#define KVM_STATE_NESTED_FORMAT_SVM	1
+4 −0
Original line number Diff line number Diff line
@@ -19,4 +19,8 @@
#define MCL_FUTURE	2		/* lock all future mappings */
#define MCL_ONFAULT	4		/* lock all pages that are faulted in */

#define SHADOW_STACK_SET_TOKEN (1ULL << 0)     /* Set up a restore token in the shadow stack */
#define SHADOW_STACK_SET_MARKER (1ULL << 1)     /* Set up a top of stack marker in the shadow stack */


#endif /* __ASM_GENERIC_MMAN_H */
+10 −1
Original line number Diff line number Diff line
@@ -841,8 +841,17 @@ __SYSCALL(__NR_lsm_list_modules, sys_lsm_list_modules)
#define __NR_mseal 462
__SYSCALL(__NR_mseal, sys_mseal)

#define __NR_setxattrat 463
__SYSCALL(__NR_setxattrat, sys_setxattrat)
#define __NR_getxattrat 464
__SYSCALL(__NR_getxattrat, sys_getxattrat)
#define __NR_listxattrat 465
__SYSCALL(__NR_listxattrat, sys_listxattrat)
#define __NR_removexattrat 466
__SYSCALL(__NR_removexattrat, sys_removexattrat)

#undef __NR_syscalls
#define __NR_syscalls 463
#define __NR_syscalls 467

/*
 * 32 bit systems traditionally used different
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