Commit 01eabef5 authored by Claudiu Beznea's avatar Claudiu Beznea Committed by Geert Uytterhoeven
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clk: renesas: rzg2l: Add support for RZ/G3S PLL 



Add support for reading the frequency of PLL1/4/6 as available on
RZ/G3S.  The computation formula for the PLL frequency is as follows:

    Fout = (nir + nfr / 4096) * Fin / (mr * pr)

Signed-off-by: default avatarClaudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230929053915.1530607-8-claudiu.beznea@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 5f710e3b

drivers/clk/renesas/rzg2l-cpg.c

+45 −4
Original line number Diff line number Diff line
@@ -47,6 +47,11 @@ 
#define PDIV(val)		FIELD_GET(GENMASK(5, 0), val)

#define SDIV(val)		FIELD_GET(GENMASK(2, 0), val)



#define RZG3S_DIV_P		GENMASK(28, 26)

#define RZG3S_DIV_M		GENMASK(25, 22)

#define RZG3S_DIV_NI		GENMASK(21, 13)

#define RZG3S_DIV_NF		GENMASK(12, 1)



#define CLK_ON_R(reg)		(reg)

#define CLK_MON_R(reg)		(0x180 + (reg))

#define CLK_RST_R(reg)		(reg)
@@ -713,11 +718,43 @@ static const struct clk_ops rzg2l_cpg_pll_ops = { 
	.recalc_rate = rzg2l_cpg_pll_clk_recalc_rate,

};



static unsigned long rzg3s_cpg_pll_clk_recalc_rate(struct clk_hw *hw,

						   unsigned long parent_rate)

{

	struct pll_clk *pll_clk = to_pll(hw);

	struct rzg2l_cpg_priv *priv = pll_clk->priv;

	u32 nir, nfr, mr, pr, val;

	u64 rate;



	if (pll_clk->type != CLK_TYPE_G3S_PLL)

		return parent_rate;



	val = readl(priv->base + GET_REG_SAMPLL_CLK1(pll_clk->conf));



	pr = 1 << FIELD_GET(RZG3S_DIV_P, val);

	/* Hardware interprets values higher than 8 as p = 16. */

	if (pr > 8)

		pr = 16;



	mr  = FIELD_GET(RZG3S_DIV_M, val) + 1;

	nir = FIELD_GET(RZG3S_DIV_NI, val) + 1;

	nfr = FIELD_GET(RZG3S_DIV_NF, val);



	rate = mul_u64_u32_shr(parent_rate, 4096 * nir + nfr, 12);



	return DIV_ROUND_CLOSEST_ULL(rate, (mr * pr));

}



static const struct clk_ops rzg3s_cpg_pll_ops = {

	.recalc_rate = rzg3s_cpg_pll_clk_recalc_rate,

};



static struct clk * __init

rzg2l_cpg_pll_clk_register(const struct cpg_core_clk *core,

			   struct clk **clks,

			   void __iomem *base,

			   struct rzg2l_cpg_priv *priv)

			   struct rzg2l_cpg_priv *priv,

			   const struct clk_ops *ops)

{

	struct device *dev = priv->dev;

	const struct clk *parent;
@@ -735,7 +772,7 @@ rzg2l_cpg_pll_clk_register(const struct cpg_core_clk *core, 


	parent_name = __clk_get_name(parent);

	init.name = core->name;

	init.ops = &rzg2l_cpg_pll_ops;

	init.ops = ops;

	init.flags = 0;

	init.parent_names = &parent_name;

	init.num_parents = 1;
@@ -830,8 +867,12 @@ rzg2l_cpg_register_core_clk(const struct cpg_core_clk *core, 
						core->mult, div);

		break;

	case CLK_TYPE_SAM_PLL:

		clk = rzg2l_cpg_pll_clk_register(core, priv->clks,

						 priv->base, priv);

		clk = rzg2l_cpg_pll_clk_register(core, priv->clks, priv->base, priv,

						 &rzg2l_cpg_pll_ops);

		break;

	case CLK_TYPE_G3S_PLL:

		clk = rzg2l_cpg_pll_clk_register(core, priv->clks, priv->base, priv,

						 &rzg3s_cpg_pll_ops);

		break;

	case CLK_TYPE_SIPLL5:

		clk = rzg2l_cpg_sipll5_register(core, priv->clks, priv);

drivers/clk/renesas/rzg2l-cpg.h

+3 −0
Original line number Diff line number Diff line
@@ -102,6 +102,7 @@ enum clk_types { 
	CLK_TYPE_IN,		/* External Clock Input */

	CLK_TYPE_FF,		/* Fixed Factor Clock */

	CLK_TYPE_SAM_PLL,

	CLK_TYPE_G3S_PLL,



	/* Clock with divider */

	CLK_TYPE_DIV,
@@ -129,6 +130,8 @@ enum clk_types { 
	DEF_TYPE(_name, _id, _type, .parent = _parent)

#define DEF_SAMPLL(_name, _id, _parent, _conf) \

	DEF_TYPE(_name, _id, CLK_TYPE_SAM_PLL, .parent = _parent, .conf = _conf)

#define DEF_G3S_PLL(_name, _id, _parent, _conf) \

	DEF_TYPE(_name, _id, CLK_TYPE_G3S_PLL, .parent = _parent, .conf = _conf)

#define DEF_INPUT(_name, _id) \

	DEF_TYPE(_name, _id, CLK_TYPE_IN)

#define DEF_FIXED(_name, _id, _parent, _mult, _div) \