Commit 01fdcbc7 authored by Paul Kocialkowski's avatar Paul Kocialkowski Committed by Chen-Yu Tsai
Browse files

clk: sunxi-ng: v3s: Fix TCON clock parents 



The TCON clock can be parented to both the video PLL and the periph0 PLL.
Add the latter, which was missing from the list.

Fixes: d0f11d14 ("clk: sunxi-ng: add support for V3s CCU")
Signed-off-by: default avatarPaul Kocialkowski <paulk@sys-base.io>
Link: https://patch.msgid.link/20250701201124.812882-5-paulk@sys-base.io


Signed-off-by: default avatarChen-Yu Tsai <wens@csie.org>
parent 2b733286

drivers/clk/sunxi-ng/ccu-sun8i-v3s.c

+1 −1
Original line number Diff line number Diff line
@@ -350,7 +350,7 @@ static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents, 
				 0x104, 0, 4, 24, 2, BIT(31),

				 CLK_SET_RATE_PARENT);



static const char * const tcon_parents[] = { "pll-video" };

static const char * const tcon_parents[] = { "pll-video", "pll-periph0" };

static SUNXI_CCU_M_WITH_MUX_GATE(tcon_clk, "tcon", tcon_parents,

				 0x118, 0, 4, 24, 3, BIT(31), 0);