Commit 045ad2c6 authored by Vincent Guittot's avatar Vincent Guittot Committed by Bjorn Helgaas
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PCI: dwc: Add register and bitfield definitions 



Add register and bitfield definitions:

  - GEN3_RELATED_OFF_EQ_PHASE_2_3 field of GEN3_RELATED_OFF

  - Coherency control registers

Signed-off-by: default avatarVincent Guittot <vincent.guittot@linaro.org>
Signed-off-by: default avatarManivannan Sadhasivam <mani@kernel.org>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: default avatarFrank Li <Frank.Li@nxp.com>
Link: https://patch.msgid.link/20251121164920.2008569-3-vincent.guittot@linaro.org
parent 0472132d

drivers/pci/controller/dwc/pcie-designware.h

+8 −0
Original line number Diff line number Diff line
@@ -121,6 +121,7 @@ 


#define GEN3_RELATED_OFF			0x890

#define GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL	BIT(0)

#define GEN3_RELATED_OFF_EQ_PHASE_2_3		BIT(9)

#define GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS	BIT(13)

#define GEN3_RELATED_OFF_GEN3_EQ_DISABLE	BIT(16)

#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT	24
@@ -138,6 +139,13 @@ 
#define GEN3_EQ_FMDC_MAX_PRE_CURSOR_DELTA	GENMASK(13, 10)

#define GEN3_EQ_FMDC_MAX_POST_CURSOR_DELTA	GENMASK(17, 14)



#define COHERENCY_CONTROL_1_OFF			0x8E0

#define CFG_MEMTYPE_BOUNDARY_LOW_ADDR_MASK	GENMASK(31, 2)

#define CFG_MEMTYPE_VALUE			BIT(0)



#define COHERENCY_CONTROL_2_OFF			0x8E4

#define COHERENCY_CONTROL_3_OFF			0x8E8



#define PCIE_PORT_MULTI_LANE_CTRL	0x8C0

#define PORT_MLTI_UPCFG_SUPPORT		BIT(7)