Commit 050e711a authored by Linus Walleij's avatar Linus Walleij
Browse files

Merge tag 'renesas-pinctrl-for-v6.18-tag1' of... 

Merge tag 'renesas-pinctrl-for-v6.18-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers

 into devel

pinctrl: renesas: Updates for v6.18

  - Add support for Output Enable (OEN) on RZ/G3E,
  - Add support for the RZ/T2H and RZ/N2H SoCs,
  - Miscellaneous fixes and improvements.

Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parents 8898cf86 d1d31e27

Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml

0 → 100644
+172 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/pinctrl/renesas,r9a09g077-pinctrl.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Renesas RZ/T2H and RZ/N2H Pin and GPIO controller



maintainers:

  - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>



description:

  The Renesas RZ/T2H and RZ/N2H SoCs feature a combined Pin and GPIO controller.

  Pin multiplexing and GPIO configuration are performed on a per-pin basis.

  Each port supports up to 8 pins, each configurable for either GPIO (port mode)

  or alternate function mode. Each pin supports function mode values ranging from

  0x0 to 0x2A, allowing selection from up to 43 different functions.



properties:

  compatible:

    enum:

      - renesas,r9a09g077-pinctrl # RZ/T2H

      - renesas,r9a09g087-pinctrl # RZ/N2H



  reg:

    minItems: 1

    items:

      - description: Non-safety I/O Port base

      - description: Safety I/O Port safety region base

      - description: Safety I/O Port Non-safety region base



  reg-names:

    minItems: 1

    items:

      - const: nsr

      - const: srs

      - const: srn



  gpio-controller: true



  '#gpio-cells':

    const: 2

    description:

      The first cell contains the global GPIO port index, constructed using the

      RZT2H_GPIO() helper macro from <dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h>

      (e.g. "RZT2H_GPIO(3, 0)" for P03_0). The second cell represents the consumer

      flag. Use the macros defined in include/dt-bindings/gpio/gpio.h.



  gpio-ranges:

    maxItems: 1



  clocks:

    maxItems: 1



  power-domains:

    maxItems: 1



definitions:

  renesas-rzt2h-n2h-pins-node:

    type: object

    allOf:

      - $ref: pincfg-node.yaml#

      - $ref: pinmux-node.yaml#

    properties:

      pinmux:

        description:

          Values are constructed from I/O port number, pin number, and

          alternate function configuration number using the RZT2H_PORT_PINMUX()

          helper macro from <dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h>.

      pins: true

      phandle: true

      input: true

      input-enable: true

      output-enable: true

    oneOf:

      - required: [pinmux]

      - required: [pins]

    additionalProperties: false



patternProperties:

  # Grouping nodes: allow multiple "-pins" subnodes within a "-group"

  '.*-group$':

    type: object

    description:

      Pin controller client devices can organize pin configuration entries into

      grouping nodes ending in "-group". These group nodes may contain multiple

      child nodes each ending in "-pins" to configure distinct sets of pins.

    additionalProperties: false

    patternProperties:

      '-pins$':

        $ref: '#/definitions/renesas-rzt2h-n2h-pins-node'



  # Standalone "-pins" nodes under client devices or groups

  '-pins$':

    $ref: '#/definitions/renesas-rzt2h-n2h-pins-node'



  '-hog$':

    type: object

    description: GPIO hog node

    properties:

      gpio-hog: true

      gpios: true

      input: true

      output-high: true

      output-low: true

      line-name: true

    required:

      - gpio-hog

      - gpios

    additionalProperties: false



allOf:

  - $ref: pinctrl.yaml#



required:

  - compatible

  - reg

  - reg-names

  - gpio-controller

  - '#gpio-cells'

  - gpio-ranges

  - clocks

  - power-domains



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h>

    #include <dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h>



    pinctrl@802c0000 {

        compatible = "renesas,r9a09g077-pinctrl";

        reg = <0x802c0000 0x2000>,

              <0x812c0000 0x2000>,

              <0x802b0000 0x2000>;

        reg-names = "nsr", "srs", "srn";

        clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKM>;

        gpio-controller;

        #gpio-cells = <2>;

        gpio-ranges = <&pinctrl 0 0 288>;

        power-domains = <&cpg>;



        serial0-pins {

            pinmux = <RZT2H_PORT_PINMUX(38, 0, 1)>, /* Tx */

                     <RZT2H_PORT_PINMUX(38, 1, 1)>; /* Rx */

        };



        sd1-pwr-en-hog {

            gpio-hog;

            gpios = <RZT2H_GPIO(39, 2) 0>;

            output-high;

            line-name = "sd1_pwr_en";

        };



        i2c0-pins {

            pins = "RIIC0_SDA", "RIIC0_SCL";

            input-enable;

        };



        sd0-sd-group {

            ctrl-pins {

                pinmux = <RZT2H_PORT_PINMUX(12, 0, 0x29)>, /* SD0_CLK */

                         <RZT2H_PORT_PINMUX(12, 1, 0x29)>; /* SD0_CMD */

            };



            data-pins {

                pinmux = <RZT2H_PORT_PINMUX(12, 0, 0x29)>, /* SD0_CLK */

                         <RZT2H_PORT_PINMUX(12, 1, 0x29)>; /* SD0_CMD */

            };

        };

    };

drivers/pinctrl/renesas/Kconfig

+13 −0
Original line number Diff line number Diff line
@@ -44,6 +44,8 @@ config PINCTRL_RENESAS 
	select PINCTRL_RZG2L if ARCH_R9A09G047

	select PINCTRL_RZG2L if ARCH_R9A09G056

	select PINCTRL_RZG2L if ARCH_R9A09G057

	select PINCTRL_RZT2H if ARCH_R9A09G077

	select PINCTRL_RZT2H if ARCH_R9A09G087

	select PINCTRL_PFC_SH7203 if CPU_SUBTYPE_SH7203

	select PINCTRL_PFC_SH7264 if CPU_SUBTYPE_SH7264

	select PINCTRL_PFC_SH7269 if CPU_SUBTYPE_SH7269
@@ -302,6 +304,17 @@ config PINCTRL_RZN1 
	help

	  This selects pinctrl driver for Renesas RZ/N1 devices.



config PINCTRL_RZT2H

	bool "pin control support for RZ/N2H and RZ/T2H" if COMPILE_TEST

	depends on 64BIT && OF

	select GPIOLIB

	select GENERIC_PINCTRL_GROUPS

	select GENERIC_PINMUX_FUNCTIONS

	select GENERIC_PINCONF

	help

	  This selects GPIO and pinctrl driver for Renesas RZ/T2H

	  platforms.



config PINCTRL_RZV2M

	bool "pin control support for RZ/V2M" if COMPILE_TEST

	depends on OF

drivers/pinctrl/renesas/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -50,6 +50,7 @@ obj-$(CONFIG_PINCTRL_RZA1) += pinctrl-rza1.o 
obj-$(CONFIG_PINCTRL_RZA2)	+= pinctrl-rza2.o

obj-$(CONFIG_PINCTRL_RZG2L)	+= pinctrl-rzg2l.o

obj-$(CONFIG_PINCTRL_RZN1)	+= pinctrl-rzn1.o

obj-$(CONFIG_PINCTRL_RZT2H)	+= pinctrl-rzt2h.o

obj-$(CONFIG_PINCTRL_RZV2M)	+= pinctrl-rzv2m.o



ifeq ($(CONFIG_COMPILE_TEST),y)

drivers/pinctrl/renesas/pinctrl-rzg2l.c

+89 −106
Original line number Diff line number Diff line
@@ -146,8 +146,6 @@ 
#define SD_CH(off, ch)		((off) + (ch) * 4)

#define ETH_POC(off, ch)	((off) + (ch) * 4)

#define QSPI			(0x3008)

#define ETH_MODE		(0x3018)

#define PFC_OEN			(0x3C40) /* known on RZ/V2H(P) only */



#define PVDD_2500		2	/* I/O domain voltage 2.5V */

#define PVDD_1800		1	/* I/O domain voltage <= 1.8V */
@@ -221,11 +219,13 @@ static const struct pin_config_item renesas_rzv2h_conf_items[] = { 
 * @pwpr: PWPR register offset

 * @sd_ch: SD_CH register offset

 * @eth_poc: ETH_POC register offset

 * @oen: OEN register offset

 */

struct rzg2l_register_offsets {

	u16 pwpr;

	u16 sd_ch;

	u16 eth_poc;

	u16 oen;

};



/**
@@ -254,6 +254,7 @@ enum rzg2l_iolh_index { 
 * @iolh_groupb_oi: IOLH group B output impedance specific values

 * @tint_start_index: the start index for the TINT interrupts

 * @drive_strength_ua: drive strength in uA is supported (otherwise mA is supported)

 * @oen_pwpr_lock: flag indicating if the OEN register is locked by PWPR

 * @func_base: base number for port function (see register PFC)

 * @oen_max_pin: the maximum pin number supporting output enable

 * @oen_max_port: the maximum port number supporting output enable
@@ -266,6 +267,7 @@ struct rzg2l_hwcfg { 
	u16 iolh_groupb_oi[4];

	u16 tint_start_index;

	bool drive_strength_ua;

	bool oen_pwpr_lock;

	u8 func_base;

	u8 oen_max_pin;

	u8 oen_max_port;
@@ -295,8 +297,7 @@ struct rzg2l_pinctrl_data { 
#endif

	void (*pwpr_pfc_lock_unlock)(struct rzg2l_pinctrl *pctrl, bool lock);

	void (*pmc_writeb)(struct rzg2l_pinctrl *pctrl, u8 val, u16 offset);

	u32 (*oen_read)(struct rzg2l_pinctrl *pctrl, unsigned int _pin);

	int (*oen_write)(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen);

	int (*pin_to_oen_bit)(struct rzg2l_pinctrl *pctrl, unsigned int _pin);

	int (*hw_to_bias_param)(unsigned int val);

	int (*bias_param_to_hw)(enum pin_config_param param);

};
@@ -322,7 +323,7 @@ struct rzg2l_pinctrl_pin_settings { 
 * @ien: IEN registers cache

 * @sd_ch: SD_CH registers cache

 * @eth_poc: ET_POC registers cache

 * @eth_mode: ETH_MODE register cache

 * @oen: Output Enable register cache

 * @qspi: QSPI registers cache

 */

struct rzg2l_pinctrl_reg_cache {
@@ -335,7 +336,7 @@ struct rzg2l_pinctrl_reg_cache { 
	u32	*pupd[2];

	u8	sd_ch[2];

	u8	eth_poc[2];

	u8	eth_mode;

	u8	oen;

	u8	qspi;

};
@@ -394,6 +395,14 @@ static const u64 r9a09g047_variable_pin_cfg[] = { 
	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 5, RZV2H_MPXED_PIN_FUNCS),

	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 6, RZV2H_MPXED_PIN_FUNCS),

	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 7, RZV2H_MPXED_PIN_FUNCS),

	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 0, RZV2H_MPXED_PIN_FUNCS),

	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_OEN),

	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 2, RZV2H_MPXED_PIN_FUNCS),

	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 3, RZV2H_MPXED_PIN_FUNCS),

	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 4, RZV2H_MPXED_PIN_FUNCS),

	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 5, RZV2H_MPXED_PIN_FUNCS),

	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 6, RZV2H_MPXED_PIN_FUNCS),

	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 7, RZV2H_MPXED_PIN_FUNCS),

	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 0, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),

	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 1, RZV2H_MPXED_PIN_FUNCS),

	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 2, RZV2H_MPXED_PIN_FUNCS),
@@ -402,6 +411,14 @@ static const u64 r9a09g047_variable_pin_cfg[] = { 
	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 5, RZV2H_MPXED_PIN_FUNCS),

	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 6, RZV2H_MPXED_PIN_FUNCS),

	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 7, RZV2H_MPXED_PIN_FUNCS),

	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 0, RZV2H_MPXED_PIN_FUNCS),

	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_OEN),

	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 2, RZV2H_MPXED_PIN_FUNCS),

	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 3, RZV2H_MPXED_PIN_FUNCS),

	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 4, RZV2H_MPXED_PIN_FUNCS),

	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 5, RZV2H_MPXED_PIN_FUNCS),

	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 6, RZV2H_MPXED_PIN_FUNCS),

	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 7, RZV2H_MPXED_PIN_FUNCS),

	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 0, RZV2H_MPXED_PIN_FUNCS),

	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),

	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 2, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
@@ -421,6 +438,14 @@ static const u64 r9a09g047_variable_pin_cfg[] = { 
	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 2, RZV2H_MPXED_PIN_FUNCS),

	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 3, RZV2H_MPXED_PIN_FUNCS),

	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 4, RZV2H_MPXED_PIN_FUNCS),

	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 0, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_OEN),

	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_OEN),

	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 2, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_OEN),

	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 3, RZV2H_MPXED_PIN_FUNCS),

	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 4, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_OEN),

	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 5, RZV2H_MPXED_PIN_FUNCS),

	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 6, RZV2H_MPXED_PIN_FUNCS),

	RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 7, RZV2H_MPXED_PIN_FUNCS),

};



static const u64 r9a09g057_variable_pin_cfg[] = {
@@ -1065,34 +1090,48 @@ static int rzg2l_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin) 
	return -EINVAL;

}



static u32 rzg2l_read_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin)

static int rzg2l_read_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin)

{

	int bit;



	bit = rzg2l_pin_to_oen_bit(pctrl, _pin);

	if (!pctrl->data->pin_to_oen_bit)

		return -EOPNOTSUPP;



	bit = pctrl->data->pin_to_oen_bit(pctrl, _pin);

	if (bit < 0)

		return 0;

		return -EINVAL;



	return !(readb(pctrl->base + ETH_MODE) & BIT(bit));

	return !(readb(pctrl->base + pctrl->data->hwcfg->regs.oen) & BIT(bit));

}



static int rzg2l_write_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen)

{

	const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs;

	u16 oen_offset = pctrl->data->hwcfg->regs.oen;

	unsigned long flags;

	u8 val, pwpr;

	int bit;

	u8 val;



	bit = rzg2l_pin_to_oen_bit(pctrl, _pin);

	if (!pctrl->data->pin_to_oen_bit)

		return -EOPNOTSUPP;



	bit = pctrl->data->pin_to_oen_bit(pctrl, _pin);

	if (bit < 0)

		return bit;

		return -EINVAL;



	spin_lock_irqsave(&pctrl->lock, flags);

	val = readb(pctrl->base + ETH_MODE);

	val = readb(pctrl->base + oen_offset);

	if (oen)

		val &= ~BIT(bit);

	else

		val |= BIT(bit);

	writeb(val, pctrl->base + ETH_MODE);

	if (pctrl->data->hwcfg->oen_pwpr_lock) {

		pwpr = readb(pctrl->base + regs->pwpr);

		writeb(pwpr | PWPR_REGWE_B, pctrl->base + regs->pwpr);

	}

	writeb(val, pctrl->base + oen_offset);

	if (pctrl->data->hwcfg->oen_pwpr_lock)

		writeb(pwpr & ~PWPR_REGWE_B, pctrl->base + regs->pwpr);

	spin_unlock_irqrestore(&pctrl->lock, flags);



	return 0;
@@ -1118,39 +1157,6 @@ static int rzg3s_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin) 
	return bit;

}



static u32 rzg3s_oen_read(struct rzg2l_pinctrl *pctrl, unsigned int _pin)

{

	int bit;



	bit = rzg3s_pin_to_oen_bit(pctrl, _pin);

	if (bit < 0)

		return bit;



	return !(readb(pctrl->base + ETH_MODE) & BIT(bit));

}



static int rzg3s_oen_write(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen)

{

	unsigned long flags;

	int bit;

	u8 val;



	bit = rzg3s_pin_to_oen_bit(pctrl, _pin);

	if (bit < 0)

		return bit;



	spin_lock_irqsave(&pctrl->lock, flags);

	val = readb(pctrl->base + ETH_MODE);

	if (oen)

		val &= ~BIT(bit);

	else

		val |= BIT(bit);

	writeb(val, pctrl->base + ETH_MODE);

	spin_unlock_irqrestore(&pctrl->lock, flags);



	return 0;

}



static int rzg2l_hw_to_bias_param(unsigned int bias)

{

	switch (bias) {
@@ -1216,55 +1222,37 @@ static int rzv2h_bias_param_to_hw(enum pin_config_param param) 
	return -EINVAL;

}



static u8 rzv2h_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin)

static int rzg2l_pin_names_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin,

				      const char * const pin_names[], unsigned int count)

{

	static const char * const pin_names[] = { "ET0_TXC_TXCLK", "ET1_TXC_TXCLK",

						  "XSPI0_RESET0N", "XSPI0_CS0N",

						  "XSPI0_CKN", "XSPI0_CKP" };

	const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[_pin];

	unsigned int i;



	for (i = 0; i < ARRAY_SIZE(pin_names); i++) {

	for (i = 0; i < count; i++) {

		if (!strcmp(pin_desc->name, pin_names[i]))

			return i;

	}



	/* Should not happen. */

	return 0;

	return -EINVAL;

}



static u32 rzv2h_oen_read(struct rzg2l_pinctrl *pctrl, unsigned int _pin)

static int rzv2h_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin)

{

	u8 bit;



	bit = rzv2h_pin_to_oen_bit(pctrl, _pin);

	static const char * const pin_names[] = {

		"ET0_TXC_TXCLK", "ET1_TXC_TXCLK", "XSPI0_RESET0N",

		"XSPI0_CS0N", "XSPI0_CKN", "XSPI0_CKP"

	};



	return !(readb(pctrl->base + PFC_OEN) & BIT(bit));

	return rzg2l_pin_names_to_oen_bit(pctrl, _pin, pin_names, ARRAY_SIZE(pin_names));

}



static int rzv2h_oen_write(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen)

static int rzg3e_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin)

{

	const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;

	const struct rzg2l_register_offsets *regs = &hwcfg->regs;

	unsigned long flags;

	u8 val, bit;

	u8 pwpr;



	bit = rzv2h_pin_to_oen_bit(pctrl, _pin);

	spin_lock_irqsave(&pctrl->lock, flags);

	val = readb(pctrl->base + PFC_OEN);

	if (oen)

		val &= ~BIT(bit);

	else

		val |= BIT(bit);



	pwpr = readb(pctrl->base + regs->pwpr);

	writeb(pwpr | PWPR_REGWE_B, pctrl->base + regs->pwpr);

	writeb(val, pctrl->base + PFC_OEN);

	writeb(pwpr & ~PWPR_REGWE_B, pctrl->base + regs->pwpr);

	spin_unlock_irqrestore(&pctrl->lock, flags);

	static const char * const pin_names[] = {

		"PB1", "PE1", "PL4", "PL1", "PL2", "PL0"

	};



	return 0;

	return rzg2l_pin_names_to_oen_bit(pctrl, _pin, pin_names, ARRAY_SIZE(pin_names));

}



static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
@@ -1308,11 +1296,10 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, 
	case PIN_CONFIG_OUTPUT_ENABLE:

		if (!(cfg & PIN_CFG_OEN))

			return -EINVAL;

		if (!pctrl->data->oen_read)

			return -EOPNOTSUPP;

		arg = pctrl->data->oen_read(pctrl, _pin);

		if (!arg)

			return -EINVAL;

		ret = rzg2l_read_oen(pctrl, _pin);

		if (ret < 0)

			return ret;

		arg = ret;

		break;



	case PIN_CONFIG_POWER_SOURCE:
@@ -1471,9 +1458,7 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, 
		case PIN_CONFIG_OUTPUT_ENABLE:

			if (!(cfg & PIN_CFG_OEN))

				return -EINVAL;

			if (!pctrl->data->oen_write)

				return -EOPNOTSUPP;

			ret = pctrl->data->oen_write(pctrl, _pin, !!arg);

			ret = rzg2l_write_oen(pctrl, _pin, !!arg);

			if (ret)

				return ret;

			break;
@@ -2058,17 +2043,17 @@ static const u64 r9a09g047_gpio_configs[] = { 
	RZG2L_GPIO_PORT_PACK(6, 0x28, RZV2H_MPXED_PIN_FUNCS),	/* P8 */

	0x0,

	RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2a),			/* PA */

	RZG2L_GPIO_PORT_PACK(8, 0x2b, RZV2H_MPXED_PIN_FUNCS),	/* PB */

	RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2b),			/* PB */

	RZG2L_GPIO_PORT_PACK(3, 0x2c, RZV2H_MPXED_PIN_FUNCS),	/* PC */

	RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2d),			/* PD */

	RZG2L_GPIO_PORT_PACK(8, 0x2e, RZV2H_MPXED_PIN_FUNCS),	/* PE */

	RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2e),			/* PE */

	RZG2L_GPIO_PORT_PACK(3, 0x2f, RZV2H_MPXED_PIN_FUNCS),	/* PF */

	RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x30),			/* PG */

	RZG2L_GPIO_PORT_PACK_VARIABLE(6, 0x31),			/* PH */

	0x0,

	RZG2L_GPIO_PORT_PACK_VARIABLE(5, 0x33),			/* PJ */

	RZG2L_GPIO_PORT_PACK(4, 0x34, RZV2H_MPXED_PIN_FUNCS),	/* PK */

	RZG2L_GPIO_PORT_PACK(8, 0x35, RZV2H_MPXED_PIN_FUNCS),	/* PL */

	RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x35),			/* PL */

	RZG2L_GPIO_PORT_PACK(8, 0x36, RZV2H_MPXED_PIN_FUNCS),	/* PM */

	0x0,

	0x0,
@@ -3164,7 +3149,7 @@ static int rzg2l_pinctrl_suspend_noirq(struct device *dev) 
	}



	cache->qspi = readb(pctrl->base + QSPI);

	cache->eth_mode = readb(pctrl->base + ETH_MODE);

	cache->oen = readb(pctrl->base + pctrl->data->hwcfg->regs.oen);



	if (!atomic_read(&pctrl->wakeup_path))

		clk_disable_unprepare(pctrl->clk);
@@ -3189,7 +3174,7 @@ static int rzg2l_pinctrl_resume_noirq(struct device *dev) 
	}



	writeb(cache->qspi, pctrl->base + QSPI);

	writeb(cache->eth_mode, pctrl->base + ETH_MODE);

	writeb(cache->oen, pctrl->base + pctrl->data->hwcfg->regs.oen);

	for (u8 i = 0; i < 2; i++) {

		if (regs->sd_ch)

			writeb(cache->sd_ch[i], pctrl->base + SD_CH(regs->sd_ch, i));
@@ -3241,6 +3226,7 @@ static const struct rzg2l_hwcfg rzg2l_hwcfg = { 
		.pwpr = 0x3014,

		.sd_ch = 0x3000,

		.eth_poc = 0x300c,

		.oen = 0x3018,

	},

	.iolh_groupa_ua = {

		/* 3v3 power source */
@@ -3256,6 +3242,7 @@ static const struct rzg2l_hwcfg rzg3s_hwcfg = { 
		.pwpr = 0x3000,

		.sd_ch = 0x3004,

		.eth_poc = 0x3010,

		.oen = 0x3018,

	},

	.iolh_groupa_ua = {

		/* 1v8 power source */
@@ -3287,8 +3274,10 @@ static const struct rzg2l_hwcfg rzg3s_hwcfg = { 
static const struct rzg2l_hwcfg rzv2h_hwcfg = {

	.regs = {

		.pwpr = 0x3c04,

		.oen = 0x3c40,

	},

	.tint_start_index = 17,

	.oen_pwpr_lock = true,

};



static struct rzg2l_pinctrl_data r9a07g043_data = {
@@ -3305,8 +3294,7 @@ static struct rzg2l_pinctrl_data r9a07g043_data = { 
#endif

	.pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock,

	.pmc_writeb = &rzg2l_pmc_writeb,

	.oen_read = &rzg2l_read_oen,

	.oen_write = &rzg2l_write_oen,

	.pin_to_oen_bit = &rzg2l_pin_to_oen_bit,

	.hw_to_bias_param = &rzg2l_hw_to_bias_param,

	.bias_param_to_hw = &rzg2l_bias_param_to_hw,

};
@@ -3322,8 +3310,7 @@ static struct rzg2l_pinctrl_data r9a07g044_data = { 
	.hwcfg = &rzg2l_hwcfg,

	.pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock,

	.pmc_writeb = &rzg2l_pmc_writeb,

	.oen_read = &rzg2l_read_oen,

	.oen_write = &rzg2l_write_oen,

	.pin_to_oen_bit = &rzg2l_pin_to_oen_bit,

	.hw_to_bias_param = &rzg2l_hw_to_bias_param,

	.bias_param_to_hw = &rzg2l_bias_param_to_hw,

};
@@ -3338,8 +3325,7 @@ static struct rzg2l_pinctrl_data r9a08g045_data = { 
	.hwcfg = &rzg3s_hwcfg,

	.pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock,

	.pmc_writeb = &rzg2l_pmc_writeb,

	.oen_read = &rzg3s_oen_read,

	.oen_write = &rzg3s_oen_write,

	.pin_to_oen_bit = &rzg3s_pin_to_oen_bit,

	.hw_to_bias_param = &rzg2l_hw_to_bias_param,

	.bias_param_to_hw = &rzg2l_bias_param_to_hw,

};
@@ -3361,8 +3347,7 @@ static struct rzg2l_pinctrl_data r9a09g047_data = { 
#endif

	.pwpr_pfc_lock_unlock = &rzv2h_pwpr_pfc_lock_unlock,

	.pmc_writeb = &rzv2h_pmc_writeb,

	.oen_read = &rzv2h_oen_read,

	.oen_write = &rzv2h_oen_write,

	.pin_to_oen_bit = &rzg3e_pin_to_oen_bit,

	.hw_to_bias_param = &rzv2h_hw_to_bias_param,

	.bias_param_to_hw = &rzv2h_bias_param_to_hw,

};
@@ -3384,8 +3369,7 @@ static struct rzg2l_pinctrl_data r9a09g056_data = { 
#endif

	.pwpr_pfc_lock_unlock = &rzv2h_pwpr_pfc_lock_unlock,

	.pmc_writeb = &rzv2h_pmc_writeb,

	.oen_read = &rzv2h_oen_read,

	.oen_write = &rzv2h_oen_write,

	.pin_to_oen_bit = &rzv2h_pin_to_oen_bit,

	.hw_to_bias_param = &rzv2h_hw_to_bias_param,

	.bias_param_to_hw = &rzv2h_bias_param_to_hw,

};
@@ -3408,8 +3392,7 @@ static struct rzg2l_pinctrl_data r9a09g057_data = { 
#endif

	.pwpr_pfc_lock_unlock = &rzv2h_pwpr_pfc_lock_unlock,

	.pmc_writeb = &rzv2h_pmc_writeb,

	.oen_read = &rzv2h_oen_read,

	.oen_write = &rzv2h_oen_write,

	.pin_to_oen_bit = &rzv2h_pin_to_oen_bit,

	.hw_to_bias_param = &rzv2h_hw_to_bias_param,

	.bias_param_to_hw = &rzv2h_bias_param_to_hw,

};

drivers/pinctrl/renesas/pinctrl-rzt2h.c

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