Commit 0685ca51 authored by Jakub Kicinski's avatar Jakub Kicinski
Browse files

Merge branch '100GbE' of git://git.kernel.org/pub/scm/linux/kernel/git/tnguy/next-queue 

Tony Nguyen says:

====================
ice: Separate TSPLL from PTP and clean up [part]

Jake Keller says:

Separate TSPLL related functions and definitions from all PTP-related
files and clean up the code by implementing multiple helpers.

* '100GbE' of git://git.kernel.org/pub/scm/linux/kernel/git/tnguy/next-queue:
  ice: add TSPLL log config helper
  ice: use designated initializers for TSPLL consts
  ice: remove ice_tspll_params_e825 definitions
  ice: fix E825-C TSPLL register definitions
  ice: rename TSPLL and CGU functions and definitions
  ice: move TSPLL functions to a separate file
====================

Link: https://patch.msgid.link/20250618174231.3100231-1-anthony.l.nguyen@intel.com


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parents 99aa0bbb 0dffcea4

drivers/net/ethernet/intel/ice/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -53,7 +53,7 @@ ice-$(CONFIG_PCI_IOV) += \ 
	ice_vf_mbx.o		\

	ice_vf_vsi_vlan_ops.o	\

	ice_vf_lib.o

ice-$(CONFIG_PTP_1588_CLOCK) += ice_ptp.o ice_ptp_hw.o ice_dpll.o

ice-$(CONFIG_PTP_1588_CLOCK) += ice_ptp.o ice_ptp_hw.o ice_dpll.o ice_tspll.o

ice-$(CONFIG_DCB) += ice_dcb.o ice_dcb_nl.o ice_dcb_lib.o

ice-$(CONFIG_RFS_ACCEL) += ice_arfs.o

ice-$(CONFIG_XDP_SOCKETS) += ice_xsk.o

drivers/net/ethernet/intel/ice/ice.h

+1 −0
Original line number Diff line number Diff line
@@ -67,6 +67,7 @@ 
#include "ice_sriov.h"

#include "ice_vf_mbx.h"

#include "ice_ptp.h"

#include "ice_tspll.h"

#include "ice_fdir.h"

#include "ice_xsk.h"

#include "ice_arfs.h"

drivers/net/ethernet/intel/ice/ice_cgu_regs.h

deleted100644 → 0
+0 −181
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0 */

/* Copyright (C) 2018-2021, Intel Corporation. */



#ifndef _ICE_CGU_REGS_H_

#define _ICE_CGU_REGS_H_



#define NAC_CGU_DWORD9 0x24

union nac_cgu_dword9 {

	struct {

		u32 time_ref_freq_sel : 3;

		u32 clk_eref1_en : 1;

		u32 clk_eref0_en : 1;

		u32 time_ref_en : 1;

		u32 time_sync_en : 1;

		u32 one_pps_out_en : 1;

		u32 clk_ref_synce_en : 1;

		u32 clk_synce1_en : 1;

		u32 clk_synce0_en : 1;

		u32 net_clk_ref1_en : 1;

		u32 net_clk_ref0_en : 1;

		u32 clk_synce1_amp : 2;

		u32 misc6 : 1;

		u32 clk_synce0_amp : 2;

		u32 one_pps_out_amp : 2;

		u32 misc24 : 12;

	};

	u32 val;

};



#define NAC_CGU_DWORD16_E825C 0x40

union nac_cgu_dword16_e825c {

	struct {

		u32 synce_remndr : 6;

		u32 synce_phlmt_en : 1;

		u32 misc13 : 17;

		u32 tspll_ck_refclkfreq : 8;

	};

	u32 val;

};



#define NAC_CGU_DWORD19 0x4c

union nac_cgu_dword19 {

	struct {

		u32 tspll_fbdiv_intgr : 8;

		u32 fdpll_ulck_thr : 5;

		u32 misc15 : 3;

		u32 tspll_ndivratio : 4;

		u32 tspll_iref_ndivratio : 3;

		u32 misc19 : 1;

		u32 japll_ndivratio : 4;

		u32 japll_iref_ndivratio : 3;

		u32 misc27 : 1;

	};

	u32 val;

};



#define NAC_CGU_DWORD22 0x58

union nac_cgu_dword22 {

	struct {

		u32 fdpll_frac_div_out_nc : 2;

		u32 fdpll_lock_int_for : 1;

		u32 synce_hdov_int_for : 1;

		u32 synce_lock_int_for : 1;

		u32 fdpll_phlead_slip_nc : 1;

		u32 fdpll_acc1_ovfl_nc : 1;

		u32 fdpll_acc2_ovfl_nc : 1;

		u32 synce_status_nc : 6;

		u32 fdpll_acc1f_ovfl : 1;

		u32 misc18 : 1;

		u32 fdpllclk_div : 4;

		u32 time1588clk_div : 4;

		u32 synceclk_div : 4;

		u32 synceclk_sel_div2 : 1;

		u32 fdpllclk_sel_div2 : 1;

		u32 time1588clk_sel_div2 : 1;

		u32 misc3 : 1;

	};

	u32 val;

};



#define NAC_CGU_DWORD23_E825C 0x5C

union nac_cgu_dword23_e825c {

	struct {

		u32 cgupll_fbdiv_intgr : 10;

		u32 ux56pll_fbdiv_intgr : 10;

		u32 misc20 : 4;

		u32 ts_pll_enable : 1;

		u32 time_sync_tspll_align_sel : 1;

		u32 ext_synce_sel : 1;

		u32 ref1588_ck_div : 4;

		u32 time_ref_sel : 1;



	};

	u32 val;

};



#define NAC_CGU_DWORD24 0x60

union nac_cgu_dword24 {

	struct {

		u32 tspll_fbdiv_frac : 22;

		u32 misc20 : 2;

		u32 ts_pll_enable : 1;

		u32 time_sync_tspll_align_sel : 1;

		u32 ext_synce_sel : 1;

		u32 ref1588_ck_div : 4;

		u32 time_ref_sel : 1;

	};

	u32 val;

};



#define TSPLL_CNTR_BIST_SETTINGS 0x344

union tspll_cntr_bist_settings {

	struct {

		u32 i_irefgen_settling_time_cntr_7_0 : 8;

		u32 i_irefgen_settling_time_ro_standby_1_0 : 2;

		u32 reserved195 : 5;

		u32 i_plllock_sel_0 : 1;

		u32 i_plllock_sel_1 : 1;

		u32 i_plllock_cnt_6_0 : 7;

		u32 i_plllock_cnt_10_7 : 4;

		u32 reserved200 : 4;

	};

	u32 val;

};



#define TSPLL_RO_BWM_LF 0x370

union tspll_ro_bwm_lf {

	struct {

		u32 bw_freqov_high_cri_7_0 : 8;

		u32 bw_freqov_high_cri_9_8 : 2;

		u32 biascaldone_cri : 1;

		u32 plllock_gain_tran_cri : 1;

		u32 plllock_true_lock_cri : 1;

		u32 pllunlock_flag_cri : 1;

		u32 afcerr_cri : 1;

		u32 afcdone_cri : 1;

		u32 feedfwrdgain_cal_cri_7_0 : 8;

		u32 m2fbdivmod_cri_7_0 : 8;

	};

	u32 val;

};



#define TSPLL_RO_LOCK_E825C 0x3f0

union tspll_ro_lock_e825c {

	struct {

		u32 bw_freqov_high_cri_7_0 : 8;

		u32 bw_freqov_high_cri_9_8 : 2;

		u32 reserved455 : 1;

		u32 plllock_gain_tran_cri : 1;

		u32 plllock_true_lock_cri : 1;

		u32 pllunlock_flag_cri : 1;

		u32 afcerr_cri : 1;

		u32 afcdone_cri : 1;

		u32 feedfwrdgain_cal_cri_7_0 : 8;

		u32 reserved462 : 8;

	};

	u32 val;

};



#define TSPLL_BW_TDC_E825C 0x31c

union tspll_bw_tdc_e825c {

	struct {

		u32 i_tdc_offset_lock_1_0 : 2;

		u32 i_bbthresh1_2_0 : 3;

		u32 i_bbthresh2_2_0 : 3;

		u32 i_tdcsel_1_0 : 2;

		u32 i_tdcovccorr_en_h : 1;

		u32 i_divretimeren : 1;

		u32 i_bw_ampmeas_window : 1;

		u32 i_bw_lowerbound_2_0 : 3;

		u32 i_bw_upperbound_2_0 : 3;

		u32 i_bw_mode_1_0 : 2;

		u32 i_ft_mode_sel_2_0 : 3;

		u32 i_bwphase_4_0 : 5;

		u32 i_plllock_sel_1_0 : 2;

		u32 i_afc_divratio : 1;

	};

	u32 val;

};



#endif /* _ICE_CGU_REGS_H_ */

drivers/net/ethernet/intel/ice/ice_common.c

+65 −4
Original line number Diff line number Diff line
@@ -2301,12 +2301,12 @@ ice_parse_1588_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 
		info->clk_freq = FIELD_GET(ICE_TS_CLK_FREQ_M, number);

		info->clk_src = ((number & ICE_TS_CLK_SRC_M) != 0);

	} else {

		info->clk_freq = ICE_TIME_REF_FREQ_156_250;

		info->clk_freq = ICE_TSPLL_FREQ_156_250;

		info->clk_src = ICE_CLK_SRC_TCXO;

	}



	if (info->clk_freq < NUM_ICE_TIME_REF_FREQ) {

		info->time_ref = (enum ice_time_ref_freq)info->clk_freq;

	if (info->clk_freq < NUM_ICE_TSPLL_FREQ) {

		info->time_ref = (enum ice_tspll_freq)info->clk_freq;

	} else {

		/* Unknown clock frequency, so assume a (probably incorrect)

		 * default to avoid out-of-bounds look ups of frequency
@@ -2314,7 +2314,7 @@ ice_parse_1588_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 
		 */

		ice_debug(hw, ICE_DBG_INIT, "1588 func caps: unknown clock frequency %u\n",

			  info->clk_freq);

		info->time_ref = ICE_TIME_REF_FREQ_25_000;

		info->time_ref = ICE_TSPLL_FREQ_25_000;

	}



	ice_debug(hw, ICE_DBG_INIT, "func caps: ieee_1588 = %u\n",
@@ -6132,3 +6132,64 @@ u32 ice_get_link_speed(u16 index) 


	return ice_aq_to_link_speed[index];

}



/**

 * ice_read_cgu_reg - Read a CGU register

 * @hw: Pointer to the HW struct

 * @addr: Register address to read

 * @val: Storage for register value read

 *

 * Read the contents of a register of the Clock Generation Unit. Only

 * applicable to E82X devices.

 *

 * Return: 0 on success, other error codes when failed to read from CGU.

 */

int ice_read_cgu_reg(struct ice_hw *hw, u32 addr, u32 *val)

{

	struct ice_sbq_msg_input cgu_msg = {

		.opcode = ice_sbq_msg_rd,

		.dest_dev = ice_sbq_dev_cgu,

		.msg_addr_low = addr

	};

	int err;



	err = ice_sbq_rw_reg(hw, &cgu_msg, ICE_AQ_FLAG_RD);

	if (err) {

		ice_debug(hw, ICE_DBG_PTP, "Failed to read CGU register 0x%04x, err %d\n",

			  addr, err);

		return err;

	}



	*val = cgu_msg.data;



	return 0;

}



/**

 * ice_write_cgu_reg - Write a CGU register

 * @hw: Pointer to the HW struct

 * @addr: Register address to write

 * @val: Value to write into the register

 *

 * Write the specified value to a register of the Clock Generation Unit. Only

 * applicable to E82X devices.

 *

 * Return: 0 on success, other error codes when failed to write to CGU.

 */

int ice_write_cgu_reg(struct ice_hw *hw, u32 addr, u32 val)

{

	struct ice_sbq_msg_input cgu_msg = {

		.opcode = ice_sbq_msg_wr,

		.dest_dev = ice_sbq_dev_cgu,

		.msg_addr_low = addr,

		.data = val

	};

	int err;



	err = ice_sbq_rw_reg(hw, &cgu_msg, ICE_AQ_FLAG_RD);

	if (err)

		ice_debug(hw, ICE_DBG_PTP, "Failed to write CGU register 0x%04x, err %d\n",

			  addr, err);



	return err;

}

drivers/net/ethernet/intel/ice/ice_common.h

+191 −0
Original line number Diff line number Diff line
@@ -39,6 +39,195 @@ 
#define FEC_RECEIVER_ID_PCS0 (0x33 << FEC_RECV_ID_SHIFT)

#define FEC_RECEIVER_ID_PCS1 (0x34 << FEC_RECV_ID_SHIFT)



#define ICE_CGU_R9 0x24

union ice_cgu_r9 {

	struct {

		u32 time_ref_freq_sel : 3;

		u32 clk_eref1_en : 1;

		u32 clk_eref0_en : 1;

		u32 time_ref_en : 1;

		u32 time_sync_en : 1;

		u32 one_pps_out_en : 1;

		u32 clk_ref_synce_en : 1;

		u32 clk_synce1_en : 1;

		u32 clk_synce0_en : 1;

		u32 net_clk_ref1_en : 1;

		u32 net_clk_ref0_en : 1;

		u32 clk_synce1_amp : 2;

		u32 misc6 : 1;

		u32 clk_synce0_amp : 2;

		u32 one_pps_out_amp : 2;

		u32 misc24 : 12;

	};

	u32 val;

};



#define ICE_CGU_R16 0x40

union ice_cgu_r16 {

	struct {

		u32 synce_remndr : 6;

		u32 synce_phlmt_en : 1;

		u32 misc13 : 17;

		u32 ck_refclkfreq : 8;

	};

	u32 val;

};



#define ICE_CGU_R19 0x4c

union ice_cgu_r19_e82x {

	struct {

		u32 fbdiv_intgr : 8;

		u32 fdpll_ulck_thr : 5;

		u32 misc15 : 3;

		u32 ndivratio : 4;

		u32 tspll_iref_ndivratio : 3;

		u32 misc19 : 1;

		u32 japll_ndivratio : 4;

		u32 japll_iref_ndivratio : 3;

		u32 misc27 : 1;

	};

	u32 val;

};



union ice_cgu_r19_e825 {

	struct {

		u32 tspll_fbdiv_intgr : 10;

		u32 fdpll_ulck_thr : 5;

		u32 misc15 : 1;

		u32 tspll_ndivratio : 4;

		u32 tspll_iref_ndivratio : 3;

		u32 misc19 : 1;

		u32 japll_ndivratio : 4;

		u32 japll_postdiv_pdivratio : 3;

		u32 misc27 : 1;

	};

	u32 val;

};



#define ICE_CGU_R22 0x58

union ice_cgu_r22 {

	struct {

		u32 fdpll_frac_div_out_nc : 2;

		u32 fdpll_lock_int_for : 1;

		u32 synce_hdov_int_for : 1;

		u32 synce_lock_int_for : 1;

		u32 fdpll_phlead_slip_nc : 1;

		u32 fdpll_acc1_ovfl_nc : 1;

		u32 fdpll_acc2_ovfl_nc : 1;

		u32 synce_status_nc : 6;

		u32 fdpll_acc1f_ovfl : 1;

		u32 misc18 : 1;

		u32 fdpllclk_div : 4;

		u32 time1588clk_div : 4;

		u32 synceclk_div : 4;

		u32 synceclk_sel_div2 : 1;

		u32 fdpllclk_sel_div2 : 1;

		u32 time1588clk_sel_div2 : 1;

		u32 misc3 : 1;

	};

	u32 val;

};



#define ICE_CGU_R23 0x5C

union ice_cgu_r23 {

	struct {

		u32 cgupll_fbdiv_intgr : 10;

		u32 ux56pll_fbdiv_intgr : 10;

		u32 misc20 : 4;

		u32 ts_pll_enable : 1;

		u32 time_sync_tspll_align_sel : 1;

		u32 ext_synce_sel : 1;

		u32 ref1588_ck_div : 4;

		u32 time_ref_sel : 1;



	};

	u32 val;

};



#define ICE_CGU_R24 0x60

union ice_cgu_r24 {

	struct {

		u32 fbdiv_frac : 22;

		u32 misc20 : 2;

		u32 ts_pll_enable : 1;

		u32 time_sync_tspll_align_sel : 1;

		u32 ext_synce_sel : 1;

		u32 ref1588_ck_div : 4;

		u32 time_ref_sel : 1;

	};

	u32 val;

};



#define TSPLL_CNTR_BIST_SETTINGS 0x344

union tspll_cntr_bist_settings {

	struct {

		u32 i_irefgen_settling_time_cntr_7_0 : 8;

		u32 i_irefgen_settling_time_ro_standby_1_0 : 2;

		u32 reserved195 : 5;

		u32 i_plllock_sel_0 : 1;

		u32 i_plllock_sel_1 : 1;

		u32 i_plllock_cnt_6_0 : 7;

		u32 i_plllock_cnt_10_7 : 4;

		u32 reserved200 : 4;

	};

	u32 val;

};



#define TSPLL_RO_BWM_LF 0x370

union tspll_ro_bwm_lf {

	struct {

		u32 bw_freqov_high_cri_7_0 : 8;

		u32 bw_freqov_high_cri_9_8 : 2;

		u32 biascaldone_cri : 1;

		u32 plllock_gain_tran_cri : 1;

		u32 plllock_true_lock_cri : 1;

		u32 pllunlock_flag_cri : 1;

		u32 afcerr_cri : 1;

		u32 afcdone_cri : 1;

		u32 feedfwrdgain_cal_cri_7_0 : 8;

		u32 m2fbdivmod_cri_7_0 : 8;

	};

	u32 val;

};



#define TSPLL_RO_LOCK_E825C 0x3f0

union tspll_ro_lock_e825c {

	struct {

		u32 bw_freqov_high_cri_7_0 : 8;

		u32 bw_freqov_high_cri_9_8 : 2;

		u32 reserved455 : 1;

		u32 plllock_gain_tran_cri : 1;

		u32 plllock_true_lock_cri : 1;

		u32 pllunlock_flag_cri : 1;

		u32 afcerr_cri : 1;

		u32 afcdone_cri : 1;

		u32 feedfwrdgain_cal_cri_7_0 : 8;

		u32 reserved462 : 8;

	};

	u32 val;

};



#define TSPLL_BW_TDC_E825C 0x31c

union tspll_bw_tdc_e825c {

	struct {

		u32 i_tdc_offset_lock_1_0 : 2;

		u32 i_bbthresh1_2_0 : 3;

		u32 i_bbthresh2_2_0 : 3;

		u32 i_tdcsel_1_0 : 2;

		u32 i_tdcovccorr_en_h : 1;

		u32 i_divretimeren : 1;

		u32 i_bw_ampmeas_window : 1;

		u32 i_bw_lowerbound_2_0 : 3;

		u32 i_bw_upperbound_2_0 : 3;

		u32 i_bw_mode_1_0 : 2;

		u32 i_ft_mode_sel_2_0 : 3;

		u32 i_bwphase_4_0 : 5;

		u32 i_plllock_sel_1_0 : 2;

		u32 i_afc_divratio : 1;

	};

	u32 val;

};



int ice_init_hw(struct ice_hw *hw);

void ice_deinit_hw(struct ice_hw *hw);

int ice_check_reset(struct ice_hw *hw);
@@ -306,4 +495,6 @@ ice_aq_write_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr, 
int ice_get_pca9575_handle(struct ice_hw *hw, u16 *pca9575_handle);

int ice_read_pca9575_reg(struct ice_hw *hw, u8 offset, u8 *data);

bool ice_fw_supports_report_dflt_cfg(struct ice_hw *hw);

int ice_read_cgu_reg(struct ice_hw *hw, u32 addr, u32 *val);

int ice_write_cgu_reg(struct ice_hw *hw, u32 addr, u32 val);

#endif /* _ICE_COMMON_H_ */