Commit 07907588 authored by Ovidiu Bunea's avatar Ovidiu Bunea Committed by Alex Deucher
Browse files

drm/amd/display: Add IPS residency capture helpers to dc_dmub_srv 



This enables starting and stopping IPS residency measurements
and querying the IPS residency information consisting of residency
percent, entry counter, total time active & inactive, and histograms
for the specified IPS mode.

Reviewed-by: default avatarNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: default avatarAric Cyr <aric.cyr@amd.com>
Signed-off-by: default avatarOvidiu Bunea <Ovidiu.Bunea@amd.com>
Signed-off-by: default avatarFangzhi Zuo <jerry.zuo@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent e9fda510

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

+78 −0
Original line number Diff line number Diff line
@@ -1862,3 +1862,81 @@ void dc_dmub_srv_fams2_passthrough_flip( 
		dm_execute_dmub_cmd_list(dc->ctx, num_cmds, cmds, DM_DMUB_WAIT_TYPE_WAIT);

	}

}



bool dc_dmub_srv_ips_residency_cntl(struct dc_dmub_srv *dc_dmub_srv, bool start_measurement)

{

	bool result;



	if (!dc_dmub_srv || !dc_dmub_srv->dmub)

		return false;



	result = dc_wake_and_execute_gpint(dc_dmub_srv->ctx, DMUB_GPINT__IPS_RESIDENCY,

					   start_measurement, NULL, DM_DMUB_WAIT_TYPE_WAIT);



	return result;

}



void dc_dmub_srv_ips_query_residency_info(struct dc_dmub_srv *dc_dmub_srv, struct ips_residency_info *output)

{

	uint32_t i;

	enum dmub_gpint_command command_code;



	if (!dc_dmub_srv || !dc_dmub_srv->dmub)

		return;



	switch (output->ips_mode) {

	case DMUB_IPS_MODE_IPS1_MAX:

		command_code = DMUB_GPINT__GET_IPS1_HISTOGRAM_COUNTER;

		break;

	case DMUB_IPS_MODE_IPS2:

		command_code = DMUB_GPINT__GET_IPS2_HISTOGRAM_COUNTER;

		break;

	case DMUB_IPS_MODE_IPS1_RCG:

		command_code = DMUB_GPINT__GET_IPS1_RCG_HISTOGRAM_COUNTER;

		break;

	case DMUB_IPS_MODE_IPS1_ONO2_ON:

		command_code = DMUB_GPINT__GET_IPS1_ONO2_ON_HISTOGRAM_COUNTER;

		break;

	default:

		command_code = DMUB_GPINT__INVALID_COMMAND;

		break;

	}



	if (command_code == DMUB_GPINT__INVALID_COMMAND)

		return;



	// send gpint commands and wait for ack

	if (!dc_wake_and_execute_gpint(dc_dmub_srv->ctx, DMUB_GPINT__GET_IPS_RESIDENCY_PERCENT,

				      (uint16_t)(output->ips_mode),

				       &output->residency_percent, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY))

		output->residency_percent = 0;



	if (!dc_wake_and_execute_gpint(dc_dmub_srv->ctx, DMUB_GPINT__GET_IPS_RESIDENCY_ENTRY_COUNTER,

				      (uint16_t)(output->ips_mode),

				       &output->entry_counter, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY))

		output->entry_counter = 0;



	if (!dc_wake_and_execute_gpint(dc_dmub_srv->ctx, DMUB_GPINT__GET_IPS_RESIDENCY_DURATION_US_LO,

				      (uint16_t)(output->ips_mode),

				       &output->total_active_time_us[0], DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY))

		output->total_active_time_us[0] = 0;

	if (!dc_wake_and_execute_gpint(dc_dmub_srv->ctx, DMUB_GPINT__GET_IPS_RESIDENCY_DURATION_US_HI,

				      (uint16_t)(output->ips_mode),

				       &output->total_active_time_us[1], DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY))

		output->total_active_time_us[1] = 0;



	if (!dc_wake_and_execute_gpint(dc_dmub_srv->ctx, DMUB_GPINT__GET_IPS_INACTIVE_RESIDENCY_DURATION_US_LO,

				      (uint16_t)(output->ips_mode),

				       &output->total_inactive_time_us[0], DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY))

		output->total_inactive_time_us[0] = 0;

	if (!dc_wake_and_execute_gpint(dc_dmub_srv->ctx, DMUB_GPINT__GET_IPS_INACTIVE_RESIDENCY_DURATION_US_HI,

				      (uint16_t)(output->ips_mode),

				       &output->total_inactive_time_us[1], DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY))

		output->total_inactive_time_us[1] = 0;



	// NUM_IPS_HISTOGRAM_BUCKETS = 16

	for (i = 0; i < 16; i++)

		if (!dc_wake_and_execute_gpint(dc_dmub_srv->ctx, command_code, i, &output->histogram[i],

					       DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY))

			output->histogram[i] = 0;

}

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h

+39 −0
Original line number Diff line number Diff line
@@ -209,4 +209,43 @@ void dc_dmub_srv_fams2_passthrough_flip( 
		struct dc_stream_state *stream,

		struct dc_surface_update *srf_updates,

		int surface_count);



/**

 * struct ips_residency_info - struct containing info from dmub_ips_residency_stats

 *

 * @ips_mode: The mode of IPS that the follow stats appertain to

 * @residency_percent: The percentage of time spent in given IPS mode in millipercent

 * @entry_counter: The number of entries made in to this IPS state

 * @total_active_time_us: uint32_t array of length 2 representing time in the given IPS mode

 *                        in microseconds. Index 0 is lower 32 bits, index 1 is upper 32 bits.

 * @total_inactive_time_us: uint32_t array of length 2 representing time outside the given IPS mode

 *                          in microseconds. Index 0 is lower 32 bits, index 1 is upper 32 bits.

 * @histogram: Histogram of given IPS state durations - bucket definitions in dmub_ips.c

 */

struct ips_residency_info {

	enum dmub_ips_mode ips_mode;

	unsigned int residency_percent;

	unsigned int entry_counter;

	unsigned int total_active_time_us[2];

	unsigned int total_inactive_time_us[2];

	unsigned int histogram[16];

};



/**

 * bool dc_dmub_srv_ips_residency_cntl() - Controls IPS residency measurement status

 *

 * @dc_dmub_srv: The DC DMUB service pointer

 * @start_measurement: Describes whether to start or stop measurement

 *

 * Return: true if GPINT was sent successfully, false otherwise

 */

bool dc_dmub_srv_ips_residency_cntl(struct dc_dmub_srv *dc_dmub_srv, bool start_measurement);



/**

 * bool dc_dmub_srv_ips_query_residency_info() - Queries DMCUB for residency info

 *

 * @dc_dmub_srv: The DC DMUB service pointer

 * @output: Output struct to copy the the residency info to

 */

void dc_dmub_srv_ips_query_residency_info(struct dc_dmub_srv *dc_dmub_srv, struct ips_residency_info *output);

#endif /* _DMUB_DC_SRV_H_ */

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

+8 −0
Original line number Diff line number Diff line
@@ -570,6 +570,14 @@ struct dmub_notification { 
	};

};



/* enum dmub_ips_mode - IPS mode identifier */

enum dmub_ips_mode {

	DMUB_IPS_MODE_IPS1_MAX		= 0,

	DMUB_IPS_MODE_IPS2,

	DMUB_IPS_MODE_IPS1_RCG,

	DMUB_IPS_MODE_IPS1_ONO2_ON

};



/**

 * DMUB firmware version helper macro - useful for checking if the version

 * of a firmware to know if feature or functionality is supported or present.

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

+95 −0
Original line number Diff line number Diff line
@@ -1050,12 +1050,107 @@ enum dmub_gpint_command { 
	 */

	DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD3 = 119,



	/**

	 * DESC: Set IPS residency measurement

	 * ARGS: 0 - Disable ips measurement

	 *       1 - Enable ips measurement

	 */

	DMUB_GPINT__IPS_RESIDENCY = 121,



	/**

	 * DESC: Enable measurements for various task duration

	 * ARGS: 0 - Disable measurement

	 *       1 - Enable measurement

	 */

	DMUB_GPINT__TRACE_DMUB_WAKE_ACTIVITY = 123,



	/**

	 * DESC: Gets IPS residency in microseconds

	 * ARGS: 0 - Return IPS1 residency

	 *       1 - Return IPS2 residency

	 *       2 - Return IPS1_RCG residency

	 *       3 - Return IPS1_ONO2_ON residency

	 * RETURN: Total residency in microseconds - lower 32 bits

	 */

	DMUB_GPINT__GET_IPS_RESIDENCY_DURATION_US_LO = 124,



	/**

	 * DESC: Gets IPS1 histogram counts

	 * ARGS: Bucket index

	 * RETURN: Total count for the bucket

	 */

	DMUB_GPINT__GET_IPS1_HISTOGRAM_COUNTER = 125,



	/**

	 * DESC: Gets IPS2 histogram counts

	 * ARGS: Bucket index

	 * RETURN: Total count for the bucket

	 */

	DMUB_GPINT__GET_IPS2_HISTOGRAM_COUNTER = 126,



	/**

	 * DESC: Gets IPS residency

	 * ARGS: 0 - Return IPS1 residency

	 *       1 - Return IPS2 residency

	 *       2 - Return IPS1_RCG residency

	 *       3 - Return IPS1_ONO2_ON residency

	 * RETURN: Total residency in milli-percent.

	 */

	DMUB_GPINT__GET_IPS_RESIDENCY_PERCENT = 127,



	/**

	 * DESC: Gets IPS1_RCG histogram counts

	 * ARGS: Bucket index

	 * RETURN: Total count for the bucket

	 */

	DMUB_GPINT__GET_IPS1_RCG_HISTOGRAM_COUNTER = 128,



	/**

	 * DESC: Gets IPS1_ONO2_ON histogram counts

	 * ARGS: Bucket index

	 * RETURN: Total count for the bucket

	 */

	DMUB_GPINT__GET_IPS1_ONO2_ON_HISTOGRAM_COUNTER = 129,



	/**

	 * DESC: Gets IPS entry counter during residency measurement

	 * ARGS: 0 - Return IPS1 entry counts

	 *       1 - Return IPS2 entry counts

	 *       2 - Return IPS1_RCG entry counts

	 *       3 - Return IPS2_ONO2_ON entry counts

	 * RETURN: Entry counter for selected IPS mode

	 */

	DMUB_GPINT__GET_IPS_RESIDENCY_ENTRY_COUNTER = 130,



	/**

	 * DESC: Gets IPS inactive residency in microseconds

	 * ARGS: 0 - Return IPS1_MAX residency

	 *       1 - Return IPS2 residency

	 *       2 - Return IPS1_RCG residency

	 *       3 - Return IPS1_ONO2_ON residency

	 * RETURN: Total inactive residency in microseconds - lower 32 bits

	 */

	DMUB_GPINT__GET_IPS_INACTIVE_RESIDENCY_DURATION_US_LO = 131,



	/**

	 * DESC: Gets IPS inactive residency in microseconds

	 * ARGS: 0 - Return IPS1_MAX residency

	 *       1 - Return IPS2 residency

	 *       2 - Return IPS1_RCG residency

	 *       3 - Return IPS1_ONO2_ON residency

	 * RETURN: Total inactive residency in microseconds - upper 32 bits

	 */

	DMUB_GPINT__GET_IPS_INACTIVE_RESIDENCY_DURATION_US_HI = 132,



	/**

	 * DESC: Gets IPS residency in microseconds

	 * ARGS: 0 - Return IPS1 residency

	 *       1 - Return IPS2 residency

	 *       2 - Return IPS1_RCG residency

	 *       3 - Return IPS1_ONO2_ON residency

	 * RETURN: Total residency in microseconds - upper 32 bits

	 */

	DMUB_GPINT__GET_IPS_RESIDENCY_DURATION_US_HI = 133,

};



/**