Commit 07f44433 authored by Michael Chan's avatar Michael Chan Committed by Jakub Kicinski
Browse files

bnxt_en: Delay for 5 seconds after AER DPC for all chips 



The FW on all chips is requiring a 5-second delay after Downstream
Port Containment (DPC) AER.  The previously added 900 msec delay was
not long enough in all cases because the chip's CRS (Configuration
Request Retry Status) mechanism is not always reliable.

Fixes: d5ab32e9 ("bnxt_en: Add delay to handle Downstream Port Containment (DPC) AER")
Reviewed-by: default avatarKalesh AP <kalesh-anakkur.purayil@broadcom.com>
Signed-off-by: default avatarMichael Chan <michael.chan@broadcom.com>
Signed-off-by: default avatarPavan Chebbi <pavan.chebbi@broadcom.com>
Link: https://patch.msgid.link/20260504083611.1383776-2-pavan.chebbi@broadcom.com


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent 5ad509c1

drivers/net/ethernet/broadcom/bnxt/bnxt.c

+8 −3
Original line number Diff line number Diff line
@@ -17360,9 +17360,14 @@ static pci_ers_result_t bnxt_io_slot_reset(struct pci_dev *pdev) 


	netdev_info(bp->dev, "PCI Slot Reset\n");



	if (!(bp->flags & BNXT_FLAG_CHIP_P5_PLUS) &&

	    test_bit(BNXT_STATE_PCI_CHANNEL_IO_FROZEN, &bp->state))

		msleep(900);

	if (test_bit(BNXT_STATE_PCI_CHANNEL_IO_FROZEN, &bp->state)) {

		/* After DPC, the chip should return CRS when the vendor ID

		 * config register is read until it is ready.  On all chips,

		 * this is not happening reliably so add a 5-second delay as a

		 * workaround.

		 */

		msleep(5000);

	}



	netdev_lock(netdev);