Commit 081bc61f authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'edac_urgent_for_v6.15_rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/ras/ras 

Pull EDAC fixes from Borislav Petkov:

 - Test the correct structure member when handling correctable errors
   and avoid spurious interrupts, in altera_edac

* tag 'edac_urgent_for_v6.15_rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/ras/ras:
  EDAC/altera: Set DDR and SDMMC interrupt mask before registration
  EDAC/altera: Test the correct error reg offset
parents 3d84c97a 6dbe3c54

drivers/edac/altera_edac.c

+5 −4
Original line number Diff line number Diff line
@@ -99,7 +99,7 @@ static irqreturn_t altr_sdram_mc_err_handler(int irq, void *dev_id) 
	if (status & priv->ecc_stat_ce_mask) {

		regmap_read(drvdata->mc_vbase, priv->ecc_saddr_offset,

			    &err_addr);

		if (priv->ecc_uecnt_offset)

		if (priv->ecc_cecnt_offset)

			regmap_read(drvdata->mc_vbase,  priv->ecc_cecnt_offset,

				    &err_count);

		edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, err_count,
@@ -1005,9 +1005,6 @@ altr_init_a10_ecc_block(struct device_node *np, u32 irq_mask, 
		}

	}



	/* Interrupt mode set to every SBERR */

	regmap_write(ecc_mgr_map, ALTR_A10_ECC_INTMODE_OFST,

		     ALTR_A10_ECC_INTMODE);

	/* Enable ECC */

	ecc_set_bits(ecc_ctrl_en_mask, (ecc_block_base +

					ALTR_A10_ECC_CTRL_OFST));
@@ -2127,6 +2124,10 @@ static int altr_edac_a10_probe(struct platform_device *pdev) 
		return PTR_ERR(edac->ecc_mgr_map);

	}



	/* Set irq mask for DDR SBE to avoid any pending irq before registration */

	regmap_write(edac->ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_SET_OFST,

		     (A10_SYSMGR_ECC_INTMASK_SDMMCB | A10_SYSMGR_ECC_INTMASK_DDR0));



	edac->irq_chip.name = pdev->dev.of_node->name;

	edac->irq_chip.irq_mask = a10_eccmgr_irq_mask;

	edac->irq_chip.irq_unmask = a10_eccmgr_irq_unmask;

drivers/edac/altera_edac.h

+2 −0
Original line number Diff line number Diff line
@@ -249,6 +249,8 @@ struct altr_sdram_mc_data { 
#define A10_SYSMGR_ECC_INTMASK_SET_OFST   0x94

#define A10_SYSMGR_ECC_INTMASK_CLR_OFST   0x98

#define A10_SYSMGR_ECC_INTMASK_OCRAM      BIT(1)

#define A10_SYSMGR_ECC_INTMASK_SDMMCB     BIT(16)

#define A10_SYSMGR_ECC_INTMASK_DDR0       BIT(17)



#define A10_SYSMGR_ECC_INTSTAT_SERR_OFST  0x9C

#define A10_SYSMGR_ECC_INTSTAT_DERR_OFST  0xA0