Commit 0881cbe0 authored by Daniele Ceraolo Spurio's avatar Daniele Ceraolo Spurio Committed by Rodrigo Vivi
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drm/xe/gsc: Query GSC compatibility version 



The version is obtained via a dedicated MKHI GSC HECI command.
The compatibility version is what we want to match against for the GSC,
so we need to call the FW version checker after obtaining the version.

Since this is the first time we send a GSC HECI command via the GSCCS,
this patch also introduces common infrastructure to send such commands
to the GSC. Communication with the GSC FW is done via input/output
buffers, whose addresses are provided via a GSCCS command. The buffers
contain a generic header and a client-specific packet (e.g. PXP, HDCP);
the clients don't care about the header format and/or the GSCCS command
in the batch, they only care about their client-specific header. This
patch therefore introduces helpers that allow the callers to
automatically fill in the input header, submit the GSCCS job and decode
the output header, to make it so that the caller only needs to worry about
their client-specific input and output messages.

v3: squash of 2 separate patches ahead of merge, so that the common
functions and their first user are added at the same time

Signed-off-by: default avatarDaniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Alan Previn <alan.previn.teres.alexis@intel.com>
Cc: Suraj Kandpal <suraj.kandpal@intel.com>
Cc: John Harrison <John.C.Harrison@Intel.com>
Reviewed-by: John Harrison <John.C.Harrison@Intel.Com> #v1
Reviewed-by: default avatarSuraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
parent f63182b4

drivers/gpu/drm/xe/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -68,6 +68,7 @@ xe-y += xe_bb.o \ 
	xe_ggtt.o \

	xe_gpu_scheduler.o \

	xe_gsc.o \

	xe_gsc_submit.o \

	xe_gt.o \

	xe_gt_clock.o \

	xe_gt_debugfs.o \

drivers/gpu/drm/xe/abi/gsc_command_header_abi.h

0 → 100644
+46 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: MIT */

/*

 * Copyright © 2023 Intel Corporation

 */



#ifndef _ABI_GSC_COMMAND_HEADER_ABI_H

#define _ABI_GSC_COMMAND_HEADER_ABI_H



#include <linux/types.h>



struct intel_gsc_mtl_header {

	u32 validity_marker;

#define GSC_HECI_VALIDITY_MARKER 0xA578875A



	u8 heci_client_id;



	u8 reserved1;



	u16 header_version;

#define MTL_GSC_HEADER_VERSION 1



	/* FW allows host to decide host_session handle as it sees fit. */

	u64 host_session_handle;



	/* handle generated by FW for messages that need to be re-submitted */

	u64 gsc_message_handle;



	u32 message_size; /* lower 20 bits only, upper 12 are reserved */



	/*

	 * Flags mask:

	 * Bit 0: Pending

	 * Bit 1: Session Cleanup;

	 * Bits 2-15: Flags

	 * Bits 16-31: Extension Size

	 * According to internal spec flags are either input or output

	 * we distinguish the flags using OUTFLAG or INFLAG

	 */

	u32 flags;

#define GSC_OUTFLAG_MSG_PENDING	BIT(0)

#define GSC_INFLAG_MSG_CLEANUP	BIT(1)



	u32 status;

} __packed;



#endif

drivers/gpu/drm/xe/abi/gsc_mkhi_commands_abi.h

0 → 100644
+39 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: MIT */

/*

 * Copyright © 2023 Intel Corporation

 */



#ifndef _ABI_GSC_MKHI_COMMANDS_ABI_H

#define _ABI_GSC_MKHI_COMMANDS_ABI_H



#include <linux/types.h>



/* Heci client ID for MKHI commands */

#define HECI_MEADDRESS_MKHI 7



/* Generic MKHI header */

struct gsc_mkhi_header {

	u8  group_id;

	u8  command;

	u8  reserved;

	u8  result;

} __packed;



/* GFX_SRV commands */

#define MKHI_GROUP_ID_GFX_SRV 0x30



#define MKHI_GFX_SRV_GET_HOST_COMPATIBILITY_VERSION (0x42)



struct gsc_get_compatibility_version_in {

	struct gsc_mkhi_header header;

} __packed;



struct gsc_get_compatibility_version_out {

	struct gsc_mkhi_header header;

	u16 proj_major;

	u16 compat_major;

	u16 compat_minor;

	u16 reserved[5];

} __packed;



#endif

drivers/gpu/drm/xe/instructions/xe_gsc_commands.h

+2 −0
Original line number Diff line number Diff line
@@ -28,6 +28,8 @@ 
	REG_FIELD_PREP(GSC_OPCODE, op) | \

	REG_FIELD_PREP(GSC_CMD_DATA_AND_LEN, dl))



#define GSC_HECI_CMD_PKT __GSC_INSTR(0, 6)



#define GSC_FW_LOAD __GSC_INSTR(1, 2)

#define   GSC_FW_LOAD_LIMIT_VALID REG_BIT(31)

drivers/gpu/drm/xe/xe_gsc.c

+82 −0
Original line number Diff line number Diff line
@@ -7,11 +7,13 @@ 


#include <drm/drm_managed.h>



#include "abi/gsc_mkhi_commands_abi.h"

#include "generated/xe_wa_oob.h"

#include "xe_bb.h"

#include "xe_bo.h"

#include "xe_device.h"

#include "xe_exec_queue.h"

#include "xe_gsc_submit.h"

#include "xe_gt.h"

#include "xe_gt_printk.h"

#include "xe_map.h"
@@ -91,6 +93,78 @@ static int emit_gsc_upload(struct xe_gsc *gsc) 
	return 0;

}



#define version_query_wr(xe_, map_, offset_, field_, val_) \

	xe_map_wr_field(xe_, map_, offset_, struct gsc_get_compatibility_version_in, field_, val_)

#define version_query_rd(xe_, map_, offset_, field_) \

	xe_map_rd_field(xe_, map_, offset_, struct gsc_get_compatibility_version_out, field_)



static u32 emit_version_query_msg(struct xe_device *xe, struct iosys_map *map, u32 wr_offset)

{

	xe_map_memset(xe, map, wr_offset, 0, sizeof(struct gsc_get_compatibility_version_in));



	version_query_wr(xe, map, wr_offset, header.group_id, MKHI_GROUP_ID_GFX_SRV);

	version_query_wr(xe, map, wr_offset, header.command,

			 MKHI_GFX_SRV_GET_HOST_COMPATIBILITY_VERSION);



	return wr_offset + sizeof(struct gsc_get_compatibility_version_in);

}



#define GSC_VER_PKT_SZ SZ_4K /* 4K each for input and output */

static int query_compatibility_version(struct xe_gsc *gsc)

{

	struct xe_uc_fw_version *compat = &gsc->fw.versions.found[XE_UC_FW_VER_COMPATIBILITY];

	struct xe_gt *gt = gsc_to_gt(gsc);

	struct xe_tile *tile = gt_to_tile(gt);

	struct xe_device *xe = gt_to_xe(gt);

	struct xe_bo *bo;

	u32 wr_offset;

	u32 rd_offset;

	u64 ggtt_offset;

	int err;



	bo = xe_bo_create_pin_map(xe, tile, NULL, GSC_VER_PKT_SZ * 2,

				  ttm_bo_type_kernel,

				  XE_BO_CREATE_SYSTEM_BIT |

				  XE_BO_CREATE_GGTT_BIT);

	if (IS_ERR(bo)) {

		xe_gt_err(gt, "failed to allocate bo for GSC version query\n");

		return PTR_ERR(bo);

	}



	ggtt_offset = xe_bo_ggtt_addr(bo);



	wr_offset = xe_gsc_emit_header(xe, &bo->vmap, 0, HECI_MEADDRESS_MKHI, 0,

				       sizeof(struct gsc_get_compatibility_version_in));

	wr_offset = emit_version_query_msg(xe, &bo->vmap, wr_offset);



	err = xe_gsc_pkt_submit_kernel(gsc, ggtt_offset, wr_offset,

				       ggtt_offset + GSC_VER_PKT_SZ,

				       GSC_VER_PKT_SZ);

	if (err) {

		xe_gt_err(gt,

			  "failed to submit GSC request for compatibility version: %d\n",

			  err);

		goto out_bo;

	}



	err = xe_gsc_read_out_header(xe, &bo->vmap, GSC_VER_PKT_SZ,

				     sizeof(struct gsc_get_compatibility_version_out),

				     &rd_offset);

	if (err) {

		xe_gt_err(gt, "HuC: invalid GSC reply for version query (err=%d)\n", err);

		return err;

	}



	compat->major = version_query_rd(xe, &bo->vmap, rd_offset, compat_major);

	compat->minor = version_query_rd(xe, &bo->vmap, rd_offset, compat_minor);



	xe_gt_info(gt, "found GSC cv%u.%u\n", compat->major, compat->minor);



out_bo:

	xe_bo_unpin_map_no_vm(bo);

	return err;

}



static int gsc_fw_is_loaded(struct xe_gt *gt)

{

	return xe_mmio_read32(gt, HECI_FWSTS1(MTL_GSC_HECI1_BASE)) &
@@ -159,6 +233,14 @@ static int gsc_upload(struct xe_gsc *gsc) 
		return err;

	}



	err = query_compatibility_version(gsc);

	if (err)

		return err;



	err = xe_uc_fw_check_version_requirements(&gsc->fw);

	if (err)

		return err;



	xe_gt_dbg(gt, "GSC FW async load completed\n");



	return 0;